CAREER: (Re)Configuring Architectures for High Performance and Low Power

随着构建包含10亿个晶体管的芯片的预期能力，更大量的存储器和功能可能在单个芯片上可用。 一个挑战是如何管理和配置所有这些资源，以实现最佳性能和功耗。 本研究探讨的问题，确定最佳使用芯片上的所有可用资源的应用程序的基础上。 在可重构逻辑可供使用的情况下（片上或片外），可以使用合成工具来确定应用的最佳硬件/软件划分，以及在架构上将硬件部分合成到可重构逻辑上。 正在开发工具来生产高性能的节能设计。 目前正在探索各种应用，以确定这些工具的有效性。这些应用程序运行在布朗计算机工程实验室设计的可重构计算平台上。低功耗和高性能的计算机设计，先进的计算机体系结构设计的主题正在通过新的课程和现有的修改引入课程。目前正在制定从大学预科到研究生各个层次为学生提供咨询和指导的方法。重点是向刚刚进入科学或工程职业的年轻妇女提供辅导和外联服务。

With the anticipated ability to build chips containing one billion transistors, a larger amount of memory and functionality may be available on a single chip. One challenge is how to manage and configure all these resources for optimal performance and power dissipation. This research explores the problem of determining optimal use of all available resources on chip on an application by application basis. Where reconfigurable logic is available for use (either on chip or off) synthesis tools can be used to determine optimal hardware/software partitioning of the application as well as to architecturally synthesize the hardware portions onto reconfigurable logic. Tools are being developed to produce high-performance power-conscious designs. Various applications are being explored to determine the effectiveness of these tools. The applications are being run on reconfigurable computing platforms designed at Brown's computer engineering laboratory. The topics of low-power and high-performance computer design, and advanced computer architecture design are being introduced to the curriculum via new courses and the modification of existing ones. Approaches to advising and mentoring students at levels from pre-college to graduate are being developed. Emphasis is in mentoring and outreach services to young women just entering a career in science or engineering.