Symbolic Techniques for Evaluating Complex Custom Circuits

本研究的重点是开发用于时序和可靠性分析的符号公式，以高效、经济的方式处理各种定制设计的复杂电路。这种符号方法能够处理任何任意电路结构，并允许有效地将电路的功能操作信息纳入分析。两个领域正在被探索：(1)符号算法正在被开发，以分析由于泄漏电流和电荷共享等原因引起的电气噪声问题。为了提高精度，分析受到时序和输入条件的约束。根据分析的结果，电路可能会被标记为设计违规或自动重新设计以提高电气可靠性。(2)建立了计算CMOS器件通道连接区（CCR）延迟的符号表达式。这些公式将处理几乎所有常用的数字电路系列，以及处理多输入转换和接受任意输入排他性约束。这项工作的目标是开发一种有效的方法来识别问题电路以进行进一步分析，同时避免需要使用其他更昂贵的仿真技术来验证许多不可实现的最坏情况。

This research focuses on the development of symbolic formulations for timing and reliability analysis that can handle a wide range of custom-designed, complex circuits in an efficient, cost-effective manner. This symbolic approach enables handling of any arbitrary circuit structure and allows for an efficient means of incorporating information on the functional operation of the circuit into the analysis.Two areas are being explored: (1) Symbolic algorithms are being developed to analyze electrical noise problems due to such things as leakage currents and charge sharing. To improve accuracy, the analysis is constrained by timing and input conditions. Based on the results of this analysis, circuits may be flagged for design violations or automatically re-designed to improve electrical reliability. (2) Symbolic formulations to calculate the delay through a channel-connected region (CCR) of CMOS devices are be developed. These formulations will handle nearly all commonly-used digital circuit families, as well as handle multiple inputs transitioning and accept arbitrary input-exclusivity constraints. The goal of this work is to develop an efficient means to identify problem circuits for further analysis while avoiding the need to verify many non-realizable worst-case conditions with other more costly simulation techniques.