NIRT: (Nanoscale Devices and System Architecture): Fault-tolerant, Probalisitic Computing with Markov Random Field Architectures and CMOS Nanodevices

NIRT：（纳米级设备和系统架构）：使用马尔可夫随机场架构和 CMOS 纳米设备进行容错、概率计算

• 批准号: 0506732
• 负责人: Ruth Bahar
• 金额: $ 31.42万
• 依托单位: Brown University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2005
• 资助国家: 美国
• 起止时间: 2005-09-01 至 2010-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0506732&HistoricalAwards=false
• 关键词: NIRT; Nanoscale; Devices; System; Architecture

NIRT: Fault-tolerant, Probabilistic Computing with Markov Random Field Architectures and CMOS NanodevicesAbstractThe project examines probabilistic design methodologies for computer architectures based on Markov random fields (MRF). The MRF approach can model arbitrary digital circuits with logic operation arising from the interaction of neighboring circuit nodes. The computation proceeds via probabilistic propagation of states through the circuit, with inputs and outputs treated on an equal footing. This approach may be particularly appropriate when dealing with the nanoscale since they are susceptible to high levels of noise. The MRF logic can be implemented in modified CMOS-based circuitry that uses output-input feedback to maximize the joint probability of correct logic states, trading off circuit area and speed for crucial fault tolerance and noise immunity. The research will map a probabilistic MRF design methodology onto CMOS, proceeding from individual devices and small combinational and sequential logic test circuits, through to higher-level architectural designs. High-end computing architectures will increasingly have to deal with issues of reliability and robustness, in the face of reduced noise margins, process variability, and manufacturing tolerances. The probabilistic design methodology being followed in this project investigates one direction to extend silicon digital logic beyond the limits imposed on standard designs by fundamental physical constraints.

NIRT：基于马尔可夫随机场体系结构和CMOS纳米器件的容错概率计算摘要该项目研究了基于马尔可夫随机场(MRF)的计算机体系结构的概率设计方法。MRF方法可以对任意数字电路进行建模，其逻辑运算源于相邻电路节点之间的相互作用。计算通过状态在电路中的概率传播来进行，输入和输出被平等对待。这种方法在处理纳米级时可能特别合适，因为它们对高水平的噪音很敏感。MRF逻辑可以在改进型基于CMOS的电路中实现，该电路使用输出输入反馈来最大限度地提高正确逻辑状态的联合概率，并在电路面积和速度之间进行权衡，以获得关键的容错性和抗噪性。这项研究将把概率MRF设计方法映射到CMOS上，从单个器件和小型组合和时序逻辑测试电路到更高级别的体系结构设计。面对更低的噪声容限、工艺可变性和制造容差，高端计算架构将越来越需要处理可靠性和健壮性问题。该项目中遵循的概率设计方法研究了一个方向，即扩展硅数字逻辑，使其超越基本物理约束对标准设计的限制。