SHF: Small: Effects of Noise in Ultimate CMOS: Modeling and Simulation Frameworks, Noise-Immune Circuit Designs, and Experimental Validation

随着近年来集成电路技术的进步，器件及其工作电压将不断缩小。这种积极的缩放趋势导致每个电路节点上的电子总数急剧减少，使电路更容易受到热噪声的影响，因此需要新的方法来估计这些电路中的噪声行为。此外，对于使用极低电源电压工作的逻辑电路来说，由于噪声边际降低，错误率预计会更高，因此对这种噪声导致的误差缓解的需求尤其迫切，这些电路专为超低功耗应用而设计。该项目将涉及研究生和本科生，包括代表性不足的群体的成员，从而将有助于扩大信息和通信技术方面的劳动力。该项目将通过三个相互关联的推力来解决最终缩放的硅基逻辑的抗噪性。第一个重点将集中在这些电路中热诱导和电压噪声诱导错误率的实验验证预测。第二个重点是开发一种新的仿真框架，用于分析噪声引起的瞬态效应。这个新框架将能够捕获罕见的故障诱导事件，比传统的模拟技术快1到3个数量级。基于从这两个初始推力中获得的发现，将开发新的具有额外噪声裕度的抗噪声逻辑门结构。此外，这些结果将用于设计新的合成工具流程，该流程将自动确定在何处以及如何最佳地使用这些抗噪声逻辑门，以达到所需的延迟、功率和可靠性要求。

With the recent advances in integrated circuit technology, devices and their operating voltages will continue to shrink. This aggressive scaling trend has the consequence of drastically reducing the total number of electrons on each circuit node, making the circuit much more susceptible to thermal noise making new approaches to estimating noise behavior in these circuits necessary. Also the need for error mitigation resulting from such noise is especially pressing for logic circuits operating using very low supply voltages, designed for ultra-low power applications, where higher error rates are expected due to the reduced noise margins. The project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.This project will address the noise immunity of ultimately scaled silicon based logic through three interrelated thrusts. The first thrust will focus on the experimentally validated prediction of thermally induced and voltage-noise induced error rates in these circuits. The second thrust involves development of a new simulation framework for analyzing transient effects due to noise. This new framework will be capable of capturing rare failure-inducing events 1 to 3 orders of magnitude faster than conventional simulation techniques. Based on the findings obtained from these two initial thrusts, new noise-immune logic gate structures that confer additional noise margin will be developed. Moreover, these results will be used to design a new synthesis tool flow, that automatically determines where and how to optimally use these noise-immune logic gates to reach desired delay, power, and reliability requirements.