SHF: Small: Effects of Noise in Ultimate CMOS: Modeling and Simulation Frameworks, Noise-Immune Circuit Designs, and Experimental Validation

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With the recent advances in integrated circuit technology, devices and their operating voltages will continue to shrink. This aggressive scaling trend has the consequence of drastically reducing the total number of electrons on each circuit node, making the circuit much more susceptible to thermal noise making new approaches to estimating noise behavior in these circuits necessary. Also the need for error mitigation resulting from such noise is especially pressing for logic circuits operating using very low supply voltages, designed for ultra-low power applications, where higher error rates are expected due to the reduced noise margins. The project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.This project will address the noise immunity of ultimately scaled silicon based logic through three interrelated thrusts. The first thrust will focus on the experimentally validated prediction of thermally induced and voltage-noise induced error rates in these circuits. The second thrust involves development of a new simulation framework for analyzing transient effects due to noise. This new framework will be capable of capturing rare failure-inducing events 1 to 3 orders of magnitude faster than conventional simulation techniques. Based on the findings obtained from these two initial thrusts, new noise-immune logic gate structures that confer additional noise margin will be developed. Moreover, these results will be used to design a new synthesis tool flow, that automatically determines where and how to optimally use these noise-immune logic gates to reach desired delay, power, and reliability requirements.