SHF: Small: Effects of Noise in Ultimate CMOS: Modeling and Simulation Frameworks, Noise-Immune Circuit Designs, and Experimental Validation

SHF：小：终极 CMOS 中的噪声影响：建模和仿真框架、抗噪声电路设计和实验验证

• 批准号: 1525486
• 负责人: Ruth Bahar
• 金额: $ 36万
• 依托单位: Brown University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-07-01 至 2020-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1525486&HistoricalAwards=false
• 关键词: SHF; Small; Effects; Noise; Ultimate

With the recent advances in integrated circuit technology, devices and their operating voltages will continue to shrink. This aggressive scaling trend has the consequence of drastically reducing the total number of electrons on each circuit node, making the circuit much more susceptible to thermal noise making new approaches to estimating noise behavior in these circuits necessary. Also the need for error mitigation resulting from such noise is especially pressing for logic circuits operating using very low supply voltages, designed for ultra-low power applications, where higher error rates are expected due to the reduced noise margins. The project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.This project will address the noise immunity of ultimately scaled silicon based logic through three interrelated thrusts. The first thrust will focus on the experimentally validated prediction of thermally induced and voltage-noise induced error rates in these circuits. The second thrust involves development of a new simulation framework for analyzing transient effects due to noise. This new framework will be capable of capturing rare failure-inducing events 1 to 3 orders of magnitude faster than conventional simulation techniques. Based on the findings obtained from these two initial thrusts, new noise-immune logic gate structures that confer additional noise margin will be developed. Moreover, these results will be used to design a new synthesis tool flow, that automatically determines where and how to optimally use these noise-immune logic gates to reach desired delay, power, and reliability requirements.

随着集成电路技术的最新进展，器件及其工作电压将继续缩小。这种积极的缩放趋势的后果是大大减少了每个电路节点上的电子总数，使电路更容易受到热噪声的影响，从而需要新的方法来估计这些电路中的噪声行为。 此外，对于使用非常低的电源电压操作的逻辑电路，特别迫切需要减轻由这种噪声引起的误差，该逻辑电路被设计用于超低功率应用，其中由于降低的噪声容限而预期更高的误差率。该项目将涉及研究生和本科生，包括代表性不足的群体的成员，因此将有助于扩大信息和通信技术的劳动力。该项目将通过三个相互关联的推力来解决最终规模化的硅基逻辑的抗噪性。第一个推力将集中在实验验证预测的热引起的和电压噪声引起的错误率在这些电路。第二个推力涉及一个新的仿真框架的发展，用于分析瞬态效应，由于噪声。 这种新框架将能够比传统仿真技术更快1到3个数量级地捕获罕见的故障诱发事件。基于从这两个初始推力获得的发现，将开发新的噪声免疫逻辑门结构，赋予额外的噪声容限。此外，这些结果将用于设计一个新的合成工具流程，自动确定在何处以及如何最佳地使用这些噪声免疫逻辑门，以达到所需的延迟，功率和可靠性要求。