CAREER: Purdue Memory Access Based Caching Schemes

CCR-9875960Vijaykumar传统上，处理器和主存储器速度之间的差距已经通过在处理器和主存储器访问之间放置包含连续级别的较慢、较大的高速缓存的高速缓冲存储器层次结构来弥合，该层次结构在层次结构的较快级别中未命中，这突显了对更好的高速缓存层次结构管理的需要。可以使用不断增加的片上晶体管来跟踪与存储器访问相关的动态信息。该项目研究新的硬件技术，以实现灵活的高速缓存管理，而不会产生过多开销。所述技术包括：(1)通过高高速缓存关联性提供灵活的管理，(2)提供从指令到高速缓存帧的快捷方式，以避免高关联性的开销，(3)通过早期执行这种地址计算来跟踪计算高速缓存未命中的地址以发起预取的指令，以及(4)跟踪访问高速缓存块的指令，以使得能够用更有用的数据替换不太有用的块。通过详细的软件模拟器测试广泛使用的基准测试来评估所提出的基于硬件的技术所实现的性能。

CCR-9875960VijaykumarTraditionally, the gap between processor and main memory speeds has been bridged by placing a hierarchy of cache memories containing successive levels of slower, larger caches between the processor and main memory accesses that miss in the faster levels of the hierarchy underscoring the need for better cache hierarchy management.The ever-increasing number of on-chip transistors can be employed to track dynamic information relevant to memory accesses. This project investigates novel hardware techniques to allow flexible cache management without excessive overheads. The techniques comprise of (1) providing flexible management through high cache associativity, (2) providing a shortcut from instructions to cache frames to avoid the overhead of high associativity, (3) tracking the instructions that compute the address of a cache miss to initiate a prefetch by executing such address computations, early, and (4) tracking the instructions that access cache blocks to enable replacement of less useful blocks by more useful data. Performance achieved by the proposed hardware-based techniques is evaluated by testing widely used benchmarks through a detailed software simulator.