CAREER: Purdue Memory Access Based Caching Schemes

职业：基于普渡内存访问的缓存方案

• 批准号: 9875960
• 负责人: T Vijaykumar
• 金额: $ 20.5万
• 依托单位: Purdue Research Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-03-01 至 2004-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9875960&HistoricalAwards=false
• 关键词: CAREER; Purdue; Memory; Access; Based

CCR-9875960VijaykumarTraditionally, the gap between processor and main memory speeds has been bridged by placing a hierarchy of cache memories containing successive levels of slower, larger caches between the processor and main memory accesses that miss in the faster levels of the hierarchy underscoring the need for better cache hierarchy management.The ever-increasing number of on-chip transistors can be employed to track dynamic information relevant to memory accesses. This project investigates novel hardware techniques to allow flexible cache management without excessive overheads. The techniques comprise of (1) providing flexible management through high cache associativity, (2) providing a shortcut from instructions to cache frames to avoid the overhead of high associativity, (3) tracking the instructions that compute the address of a cache miss to initiate a prefetch by executing such address computations, early, and (4) tracking the instructions that access cache blocks to enable replacement of less useful blocks by more useful data. Performance achieved by the proposed hardware-based techniques is evaluated by testing widely used benchmarks through a detailed software simulator.

传统上，处理器和主存储器速度之间的差距已经通过放置高速缓冲存储器的层次结构而被桥接，该高速缓冲存储器包含连续的较慢、较慢、较低和较低级别，在处理器和主存储器访问之间的较大高速缓存在层次结构的较快级别中未命中，这强调了对更好的高速缓存层次结构管理的需要。可以采用芯片晶体管来跟踪与存储器访问相关的动态信息。 本项目研究新的硬件技术，允许灵活的高速缓存管理，而不会产生过多的开销。 所述技术包括（1）通过高高速缓存关联性提供灵活的管理，（2）提供从指令到高速缓存帧的快捷方式以避免高关联性的开销，（3）跟踪计算高速缓存未命中的地址的指令，以通过尽早执行这样的地址计算来启动预取，以及（4）跟踪访问高速缓存块的指令，以使得能够用更有用的数据替换不太有用的块。 所提出的基于硬件的技术实现的性能进行评估，通过测试广泛使用的基准，通过详细的软件模拟器。