Collaborative research: Architecture and Prototype for a Programmable Lab-on-a-Chip

片上实验室(LoC)技术使传统的实验室规模的实验能够小型化并集成到单个芯片上，该芯片包括芯片上的组件，如通道、阀门和混合器。目前，LOC被设计为特定于应用的芯片，其中通过创建和连接芯片上的组件来匹配分析的步骤，为每种分析设计一个新的LOC。(即，n个分析需要n个LOC设计)。不幸的是，这种特定于应用的方法(1)引起了大量的设计工作、周转时间和每次分析的成本，以及(2)降低了生产率，因为它需要LoC工程师知道分析的细节，并且LoC的用户需要知道LoC的限制。为了解决这些限制，这个项目将设计和原型一个通用的、可编程的LoC(PLoC)，它不实现任何特定的分析，而是使用软件将分析转换为在PLoC上运行的等效的“可执行文件”。可执行程序将化验分解为一系列称为“流体指令”的基本步骤，这些步骤在硬件中实现。PLoC执行的流体指令集称为其“流体指令集”，如果可以使用PLoC的流体指令集翻译分析，则可以在PLoC上执行任何分析(即，n个分析使用1个PLoC设计，而不需要n个LOC设计)。与LOCS相比，PLoC由于单芯片的一次性设计而显著降低了设计工作量和更快的周转时间，并且由于体积经济而降低了成本。流体指令集和软件翻译器(称为“流体编译器”)实现了硬件和分析之间的清晰分离，极大地提高了LoC用户和LoC工程师的工作效率。

Lab-on-a-chip (LoC) technology has enabled miniaturization and integration of conventional bench-scale experiments to a single chip comprising on-chip components, such as channels, valves, and mixers. Currently, LoCs are designed as application-specific chips, where a new LoC is designed for every assay by creating and connecting on-chip components to match the steps of the assay. (i.e., n assays need n LoC designs). Unfortunately, this application-specific approach (1) incurs considerable design effort, turn-around time, and cost for each assay and (2) reduces productivity because it requires LoC engineers to know the assay specifics and LoC users to know the constraints of the LoC.To address these limitations, this project will design and prototype a general-purpose, programmable LoC (PLoC) which does not implement any specific assay and instead employs software to translate an assay into an equivalent "executable" which is run on the PLoC. The executable breaks down the assay into a sequence of basic steps called "fluid instructions", which are implemented in hardware. The set of fluid instructions implemented by a PLoC is called its "fluid instruction set", and any assay can be executed on the PLoC if the assay can be translated using the PLoC's fluid instruction set (i.e., n assays use 1 PLoC design instead of requiring n LoC designs). Compared to LoCs, the PLoC has significantly lower design effort and faster turn-around time due to one-time design of a single chip, and lower cost due to economy of volume. The clean separation between hardware and assay achieved by the fluid instruction set and the software translator (called "the fluidic compiler") vastly improves the productivity of LoC users and LoC engineers.