SHF: Small: Light-weight Architectural Schemes for Resilient High-performance Microprocessors

SHF：小型：弹性高性能微处理器的轻量级架构方案

• 批准号: 1320263
• 负责人: T Vijaykumar
• 金额: $ 49.28万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-07-01 至 2017-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320263&HistoricalAwards=false
• 关键词: SHF; Small; Light; weight; Architectural

In future technology generations, smaller and more transistors operating at low supply voltages and high clock speeds will be increasingly susceptible to many different resiliency problems, such as soft errors, wear-out issues, hard errors, and off- and on-chip bus bit errors. These errors may cause silent data corruption, application aborts, or system crashes in high-performance microprocessors and computer systems. Previous techniques for addressing these errors incur significant performance and power overheads despite optimizations, and often require invasive changes that incur high implementation complexity.In this research project, the investigators propose a novel, light-weight, yet highly-effective architectural approach to processor reliability that incurs much lower overheads than existing approaches by leveraging key architectural observations about the problems.This project's innovative approach for the detection of soft errors, wear-out, and hard errors is based on detecting execution anomalies that are triggered by errors, without using redundant execution. By exploiting the notion of value locality, this project generalizes anomalies to include unexpected values as well as conditions (e.g., memory access exceptions) and provides significant coverage which includes the most problematic cases of silent data corruption. For recovery from soft errors, the project's investigators propose a retry-based scheme that avoids adding any hardware overhead to achieve recovery by using existing spare speculative resources in the processor. For off-chip bus bit errors, the investigators propose a novel bit interleaving scheme that reduces the chances of multiple bits in a single error correcting code (ECC)-protected data unit being corrupted undetectably or uncorrectably. Like the other schemes, thisinterleaving imposes minimal power, performance, and complexity overhead.This project targets achieving reliability while keeping power, performance, and hardware overheads low, an important goal for the U.S. microprocessor and computer hardware industry. The project's investigators are committed to releasing the research artifacts as open-source software to be used by the research community. The graduate students working on this project will be trained in architecture and reliability issues and will be well-positioned to join the U.S. computer hardware industry. This project will also support educational activities such as homework and term projects in undergraduate and graduate courses as well as outreach activities of various centers at Purdue with which the investigators are involved. With a woman as one of the investigators, the project will act as a basis for encouraging women to join graduate programs in electrical and computer engineering.

在未来的技术世代中，在低电源电压和高时钟速度下工作的更小、更多的晶体管将越来越容易受到许多不同的弹性问题的影响，例如软错误、磨损问题、硬错误以及片内和片外总线位错误。这些错误可能会导致高性能微处理器和计算机系统中的静默数据损坏、应用程序中止或系统崩溃。以前用于解决这些错误的技术尽管进行了优化，但会导致显著的性能和功率开销，并且通常需要进行侵入性更改，从而导致实现的高度复杂性。在这个研究项目中，研究人员提出了一种新颖的、轻量级的、高效的处理器可靠性体系结构方法，通过利用对问题的关键体系结构观察，该方法比现有方法的开销要低得多。这个项目用于检测软错误、损耗和硬错误的创新方法是基于检测由错误触发的执行异常，而不使用冗余执行。通过利用值局域性的概念，该项目概括了异常，包括意外值和条件（例如，内存访问异常），并提供了很大的覆盖范围，其中包括无声数据损坏的最有问题的情况。对于从软错误中恢复，该项目的研究人员提出了一种基于重试的方案，通过使用处理器中现有的备用推测资源来避免增加任何硬件开销以实现恢复。对于片外总线位错误，研究人员提出了一种新颖的位交错方案，该方案减少了单个纠错码（ECC）保护的数据单元中多个位被不可检测或不可纠正地损坏的机会。与其他方案一样，这种交错会带来最小的功耗、性能和复杂性开销。该项目的目标是实现可靠性，同时保持低功耗、性能和硬件开销，这是美国微处理器和计算机硬件行业的一个重要目标。该项目的研究人员承诺将研究工件作为开源软件发布，供研究社区使用。从事该项目的研究生将接受架构和可靠性问题方面的培训，并将为加入美国计算机硬件行业做好准备。该项目还将支持教育活动，如本科和研究生课程的家庭作业和学期项目，以及研究人员参与的普渡大学各个中心的外展活动。研究人员中有一名女性，该项目将作为鼓励女性参加电气和计算机工程研究生课程的基础。