CCF: SHF Small: Coping with the Slowing of Dennard's Scaling

控制CMOS集成芯片的功率、电压和频率增长的Dennard缩放比例与摩尔定律一样有助于实现芯片上有源晶体管数量的指数增长。不幸的是，最近Dennard在未来多核中对电源电压的缩放速度减慢，可能会导致暗硅，其中越来越多的核由于缺乏电源而必须保持断电。一种替代方案是通过针对特定功能定制内核来提高功率效率。虽然暗硅选项显然会降低性能，但定制选项会使多核走上一条潜在的艰难道路，增加硬件设计、验证和测试的工作量，并降低可编程性。架构师面临的挑战是围绕Dennard缩放速度放缓的现实进行设计，同时避免两种严重后果（暗硅或定制核心设计的成本/工作量增加）。该项目通过追求替代方案解决了上述挑战，温和（即，不费力的）路径，同时保持在由Dennard缩放的减慢所施加的功率包络内。该设计采用连续的频率缩放，其中所有内核都保持供电，并且每一代都以连续较慢的时钟运行，以保持在功率预算内。 一个分析模型（作为本项目的一部分开发）的系统的性能与连续的频率不缩放，使令人惊讶的预测，尽管相当慢的时钟在以后的几代（例如，sub-GHz），连续的频率去定标将超过暗硅性能极限。该项目的主要研究目标是通过真实的应用和详细的系统仿真来验证模型的预测。验证一种替代的、温和的多核扩展路径有可能为微处理器和计算机行业带来重大利益。除了研究的影响，该项目在研究生和本科课程的教育组成部分的整合有助于扩大其教育影响。

Dennard's scaling, which governs the growth of power, voltage and frequency of CMOS integrated chips, has been as instrumental as Moore's law in enabling the exponential growth of the number of active transistors on a chip. Unfortunately, the recent slowing down of Dennard's scaling of the supply voltage in future multicores may result in dark silicon where an increasing number of cores must be kept powered down due to lack of power. One alternative is to improve power efficiency by customizing the cores for specific functionalities. While the dark silicon option obviously degrades performance, the customization option puts multicores on a potentially arduous path of increased effort for hardware design, verification, and test, and degraded programmability. The challenge that architects face is to design around the reality of the slowing of Dennard's scaling while avoiding either of the two harsh consequences (dark silicon, or the increased cost/effort of customized core design).This project addresses the above challenge by pursuing an alternative, gentle (i.e., non-arduous) path for multicore scaling, while remaining within the power envelope imposed by the slowing of Dennard's scaling. The design employs successive frequency unscaling, where all the cores are kept powered and run at successively slower clocks every generation to stay within the power budget. An analytical model (developed as part of this project) for the performance of systems with and without successive frequency unscaling makes the surprising prediction that despite considerably slower clocks in later generations (e.g., sub-GHz), successive frequency unscaling would exceed the dark silicon performance limit. The key research goal of this project is to validate the predictions of the model with real applications and detailed system simulation. Validating an alternative, gentle path for multicore scaling has the potential to offer significant benefits for the microprocessor and computer industry. Beyond the research impacts, the project's integration of education components in both graduate and undergraduate curricula helps expand its educational impact.