CISE Experimental Partnerships: An Experimental Configurable Computing System for Wireless Communications

99- 01377 Ebeling，CarlHui，Liu华盛顿大学CISE实验合作伙伴关系：一个实验性的可配置计算系统的无线通信一个实验性的可配置计算系统的基础上的RaPiD架构正在建设，将展示粗粒度的可配置计算架构在信号和图像处理领域的优势。 这项工作涉及的建设，示范和分析的原型智能天线CDMA无线基站使用这个实验systems.The重点的研究是RaPiD可配置架构的仿真使用大型Xilinx的Virtex FPGA，最近已经成为可用。 该RaPiD仿真系统具有与作为该架构的最终目标的单芯片RaPiD系统相同的功能。 仿真的目标是在目标速度为50 MHz时具有足够的性能，以演示CDMA无线基站等实时应用。 RaPiD架构的每个组件都使用FPGA进行仿真，包括数据路径、数据路径控制器、流控制器和存储器控制器。 这个实验系统被用来模拟最终的RaPiD架构。 也就是说，FPGA以受RaPiD架构约束的方式操作，以便提供RaPiD架构的成本和性能的准确测量。 该仿真系统提供了探索与RaPiD相关的许多替代架构和系统想法的机会。 这种探索可能导致RaPiD架构作为片上系统技术中的计算核心的有效定义。

99-01377Ebeling, CarlHui, LiuUniversity of WashingtonCISE Experimental Partnerships: An Experimental Configurable ComputingSystem for Wireless CommunicationAn experimental configurable computing system based on the RaPiD architecture is being constructed that will demonstrate the advantages of coarse-grained configurable computing architectures in the domain of signal and image processing. The work involves the construction, demonstration and analysis of a prototype smart antenna CDMA wireless basestation using this experimental system.The focus of this research is the emulation of the RaPiD configurable architecture using the large Xilinx Virtex FPGAs that have recently become available. This RaPiD Emulation System has the same functionality as a single-chip RaPiD system that is the eventual target of this architecture. The goal is for the emulation to have sufficient performance running at a target speed of 50 MHz to demonstrate real-time applications such as the CDMA wireless basestation. Each component of the RaPiD architecture is emulated using FPGAs, including the datapath, the datapath controller, the stream controllers and the memory controller. This experimental system is being used to emulate the final RaPiD architecture. That is, the FPGAs are operated in a way that is constrained by the RaPiD architecture in order to provide an accurate measure of the cost and performance of the RaPiD architecture. This emulation system provides opportunities to explore many alternative architectural and system ideas related to RaPiD. This exploration could lead to an efficient definition of the RaPiD architecture as a computational core in system-on-a-chip technology.