CISE Experimental Partnerships: Prototyping the Superthreaded Architecture

9971666 Lilja，David Jew，明尼苏达大学Pen-ChungUniversity-Twin CitiesCISE实验伙伴关系：原型超线程处理器体系结构(实验伙伴关系)这项研究试图通过探索新的编译器技术和计算机体系结构，在指令级别和线程级别发现程序中足够的并行性。超线程处理器体系结构通过利用编译器辅助的跨线程运行时数据相关性检查来支持指令级和线程级推测，从而同时利用应用程序中的多粒度并行性。这项研究使用基于软件的仿真工具，使用硬件描述语言实现来验证超线程体系结构，作为迈向更详细的基于循环的仿真的一步。一个用于C和Fortran的集成并行化编译器正在开发中，以支持使用实际基准程序的测试。正在研究对超线程体系结构和编译技术的扩展，以利用另一个线程维度来扩展额外的并行性，以更有效地隐藏内存延迟。针对扩展的超线程体系结构，正在对现有的集成并行化编译器进行重大增强，以解决可伸缩性和内存延迟隐藏问题。这个项目中开发的新编译器技术也将使现有的大问题超标量处理器受益，因为利用C程序中的线程级并行性和延迟隐藏的技术至今仍处于初级阶段。此外，正在开发一个完整的基础设施，以研究并发多线程体系结构的体系结构和编译器技术之间的交互，这些体系结构利用不同级别的并行性和可伸缩性和内存延迟隐藏的推测。这个实验基础设施包括集成的并行化编译器、到快速仿真工具的接口，以及完全基于执行的模拟器。

9971666Lilja, David JYew, Pen-ChungUniversity of Minnesota-Twin CitiesCISE Experimental Partnerships: Prototyping the Superthreaded ProcessorArchitecture (Experimental Partnerships)This research seeks to discover sufficient parallelism in programs both at the instruction-level and at the thread-level by exploring new compiler technologies and computer architectures. The superthreaded processor architecture simultaneously exploits multiple granularities of parallelism in application programs by supporting both instruction-level and thread-level speculation with compiler-assisted cross-thread runtime data dependence checking. This research validates the superthreaded architecture with a hardware description language implementation using a software-based emulation facility as a step towards a more detailed cycle-based emulation. An integrated parallelizing compiler for both C and Fortran is being developed to support tests using realistic benchmark programs. Extensions to the superthreaded architecture and compilation techniques are being investigated to exploit another thread dimension to expend additional parallelism to more effectively hide memory latency. Significant enhancements are being made to the existing integrated parallelizing compiler to target the extended superthreaded architecture to address both the scalability and the memory latency hiding issues. The new compiler techniques developed in this project will also benefit existing wide-issue superscalar processors since techniques to exploit thread-level parallelism and latency hiding in C programs are still in their infancy today. Additionally, a complete infrastructure is being developed to study the interaction between architecture and compiler techniques for concurrent multithreaded architectures that exploit various levels of parallelism and speculation for both scalability and memory latency hiding. This experimental infrastructure includes the integrated parallelizing compiler, an interface to a fast emulation facility, and a complete execution-based simulator.