CISE Experimental Partnerships: Prototyping the Superthreaded Architecture

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9971666Lilja, David JYew, Pen-ChungUniversity of Minnesota-Twin CitiesCISE Experimental Partnerships: Prototyping the Superthreaded ProcessorArchitecture (Experimental Partnerships)This research seeks to discover sufficient parallelism in programs both at the instruction-level and at the thread-level by exploring new compiler technologies and computer architectures. The superthreaded processor architecture simultaneously exploits multiple granularities of parallelism in application programs by supporting both instruction-level and thread-level speculation with compiler-assisted cross-thread runtime data dependence checking. This research validates the superthreaded architecture with a hardware description language implementation using a software-based emulation facility as a step towards a more detailed cycle-based emulation. An integrated parallelizing compiler for both C and Fortran is being developed to support tests using realistic benchmark programs. Extensions to the superthreaded architecture and compilation techniques are being investigated to exploit another thread dimension to expend additional parallelism to more effectively hide memory latency. Significant enhancements are being made to the existing integrated parallelizing compiler to target the extended superthreaded architecture to address both the scalability and the memory latency hiding issues. The new compiler techniques developed in this project will also benefit existing wide-issue superscalar processors since techniques to exploit thread-level parallelism and latency hiding in C programs are still in their infancy today. Additionally, a complete infrastructure is being developed to study the interaction between architecture and compiler techniques for concurrent multithreaded architectures that exploit various levels of parallelism and speculation for both scalability and memory latency hiding. This experimental infrastructure includes the integrated parallelizing compiler, an interface to a fast emulation facility, and a complete execution-based simulator.