CISE Experimental Partnerships: Prototyping the Superthreaded Architecture

CISE 实验合作伙伴：超线程架构原型设计

• 批准号: 9971666
• 负责人: David Lilja
• 金额: $ 93.25万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-15 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9971666&HistoricalAwards=false
• 关键词: CISE; Experimental; Partnerships; Prototyping; Superthreaded

9971666Lilja, David JYew, Pen-ChungUniversity of Minnesota-Twin CitiesCISE Experimental Partnerships: Prototyping the Superthreaded ProcessorArchitecture (Experimental Partnerships)This research seeks to discover sufficient parallelism in programs both at the instruction-level and at the thread-level by exploring new compiler technologies and computer architectures. The superthreaded processor architecture simultaneously exploits multiple granularities of parallelism in application programs by supporting both instruction-level and thread-level speculation with compiler-assisted cross-thread runtime data dependence checking. This research validates the superthreaded architecture with a hardware description language implementation using a software-based emulation facility as a step towards a more detailed cycle-based emulation. An integrated parallelizing compiler for both C and Fortran is being developed to support tests using realistic benchmark programs. Extensions to the superthreaded architecture and compilation techniques are being investigated to exploit another thread dimension to expend additional parallelism to more effectively hide memory latency. Significant enhancements are being made to the existing integrated parallelizing compiler to target the extended superthreaded architecture to address both the scalability and the memory latency hiding issues. The new compiler techniques developed in this project will also benefit existing wide-issue superscalar processors since techniques to exploit thread-level parallelism and latency hiding in C programs are still in their infancy today. Additionally, a complete infrastructure is being developed to study the interaction between architecture and compiler techniques for concurrent multithreaded architectures that exploit various levels of parallelism and speculation for both scalability and memory latency hiding. This experimental infrastructure includes the integrated parallelizing compiler, an interface to a fast emulation facility, and a complete execution-based simulator.

9971666 Lilja，大卫JYew，Pen-Chung明尼苏达大学双城分校CISE实验伙伴关系：原型化的超线程处理器架构（实验伙伴关系）这项研究旨在发现足够的并行程序在编译级别和线程级别通过探索新的编译器技术和计算机体系结构。 超线程处理器体系结构同时利用多粒度的并行应用程序，通过支持编译器辅助跨线程运行时数据依赖检查的并行级和线程级的推测。本研究验证了超线程架构与硬件描述语言实现使用基于软件的仿真设施作为一个更详细的基于周期的仿真的一步。 一个集成的并行编译器为C和Fortran正在开发支持测试使用现实的基准程序。 正在研究对超线程架构和编译技术的扩展，以利用另一个线程维度来消耗额外的并行性，从而更有效地隐藏内存延迟。 正在对现有的集成并行化编译器进行显著的增强，以针对扩展的超线程架构来解决可扩展性和存储器延迟隐藏问题。 在这个项目中开发的新的编译器技术也将有利于现有的广泛发行超标量处理器，因为利用线程级并行性和C程序中隐藏的延迟的技术今天仍然处于起步阶段。 此外，一个完整的基础设施正在开发中，研究架构和编译器技术之间的相互作用，利用各种级别的并行性和投机的可扩展性和内存延迟隐藏的并发多线程架构。 这个实验基础设施包括集成的并行化编译器，一个接口的快速仿真设施，和一个完整的基于执行的模拟器。