Compiling for Explicitly Parallel Adaptable Architectures

编译显式并行自适应架构

• 批准号: 0220095
• 负责人: Carl Ebeling
• 金额: $ 30万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-09-01 至 2006-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0220095&HistoricalAwards=false
• 关键词: Compiling; Explicitly; Parallel; Adaptable; Architectures

As the demands on portable embedded systems increase with the incorporation of high-bandwidth wireless data along with multimedia and speech processing, it is becoming increasingly difficult to achieve the required performance and power requirements with programmable solutions. Current platforms for high-end embedded systems typically comprise one or more RISC or DSP processors, along with an increasing number of application-specific (ASIC) components that are necessary to deliver high performance at low power. As more and more functionality is implemented using ASIC components, the platform's range of application decreases and its vulnerability to obsolescence increases.Coarse-grained adaptable architectures bridge the gap between traditional processors and ASIC solutions and can be used to replace many of the ASIC components in high-performance embedded platforms. The goal of this research is to make these adaptable architectures accessible to programmers via a high-level programming language interface. This project will develop a compiler comprising a standard front-end combined with a parallelizing backend that performs scheduling and optimization using a simultaneous place and route algorithm based on those used in physical design automation. Posing the scheduling problem as a place and route problem allows the many constraints imposed by adaptable architectures to be solved by a single phase of the compiler.

随着对便携式嵌入式系统的需求随着高带宽无线数据沿着多媒体和语音处理的结合而增加，利用可编程解决方案来实现所需的性能和功耗要求变得越来越困难。 用于高端嵌入式系统的当前平台通常包括一个或多个RISC或DSP处理器，以及沿着增加数量的专用（ASIC）组件，这些专用组件是以低功率提供高性能所必需的。 随着越来越多的功能使用ASIC组件来实现，平台的应用范围越来越小，其过时的脆弱性也越来越大。粗粒度的自适应架构弥合了传统处理器和ASIC解决方案之间的差距，可以用来取代高性能嵌入式平台中的许多ASIC组件。 这项研究的目标是使这些适应性强的架构，通过一个高级编程语言接口的程序员访问。 该项目将开发一个编译器，包括一个标准的前端与并行后端相结合，使用基于物理设计自动化中使用的同步布局和路由算法执行调度和优化。 将调度问题作为一个位置和路线问题，允许由自适应架构施加的许多约束由编译器的单个阶段来解决。