Compiling for Explicitly Parallel Adaptable Architectures

随着对便携式嵌入式系统的需求随着高带宽无线数据以及多媒体和语音处理的结合而增加，使用可编程解决方案来实现所需的性能和功耗要求变得越来越困难。当前的高端嵌入式系统平台通常包括一个或多个RISC或DSP处理器，以及越来越多的专用（ASIC）组件，这些组件是在低功耗下提供高性能所必需的。随着越来越多的功能使用ASIC组件实现，平台的应用范围越来越小，其过时的脆弱性也越来越大。粗粒度适应性架构弥补了传统处理器和ASIC解决方案之间的差距，可用于取代高性能嵌入式平台中的许多ASIC组件。本研究的目标是使程序员能够通过高级编程语言接口访问这些可适应的体系结构。该项目将开发一个编译器，包括一个标准前端和一个并行后端，该后端使用基于物理设计自动化中使用的同步放置和路由算法执行调度和优化。将调度问题作为一个位置和路径问题，允许由适应性体系结构施加的许多约束通过编译器的一个阶段来解决。

As the demands on portable embedded systems increase with the incorporation of high-bandwidth wireless data along with multimedia and speech processing, it is becoming increasingly difficult to achieve the required performance and power requirements with programmable solutions. Current platforms for high-end embedded systems typically comprise one or more RISC or DSP processors, along with an increasing number of application-specific (ASIC) components that are necessary to deliver high performance at low power. As more and more functionality is implemented using ASIC components, the platform's range of application decreases and its vulnerability to obsolescence increases.Coarse-grained adaptable architectures bridge the gap between traditional processors and ASIC solutions and can be used to replace many of the ASIC components in high-performance embedded platforms. The goal of this research is to make these adaptable architectures accessible to programmers via a high-level programming language interface. This project will develop a compiler comprising a standard front-end combined with a parallelizing backend that performs scheduling and optimization using a simultaneous place and route algorithm based on those used in physical design automation. Posing the scheduling problem as a place and route problem allows the many constraints imposed by adaptable architectures to be solved by a single phase of the compiler.