Multiprocessor Memory Design for High-Performance Computing

为了使计算机系统性能得到显著提高，以解决“重大挑战”计算问题，有必要在新的计算机设计中加入更多的并行处理技术。然而，在多处理器中实现高性能的一个主要障碍是访问数据内存时遇到的延迟。当前用于减少内存延迟的技术，如数据预取、矢量内存提取和私有数据缓存，在多处理器中并不像在传统的单处理器中那样有效，因为它们无法使用所有可用的信息。特别是，这些技术通常只依赖于运行时可用的信息，这在多处理器系统的复杂环境中是不够的。本研究项目的主要目标是开发和分析通过集成硬件和软件策略来利用所有内存参考信息来提高多处理器内存性能的新技术。该项目将探索编译时的语义信息和运行时的动态信息，以改进数据预取、处理器调度、数据放置和缓存一致性执行。通过这项研究产生的新技术将通过跟踪驱动仿真、数学模型、在实际并行机器上运行的软件原型以及在并行编译器中实现新算法的独特组合来验证。

To produce the dramatic increases in computer system performance needed to solve the "grand challenge" computational problems, it will be necessary to incorporate more parallel processing technology into new computer designs. A major impediment to achieving high performance in a multiprocessor, however, is the delay encountered when accessing the data memory. Current techniques for reducing the memory delay, such as data prefetching, vector memory fetches, and private data caches, have not been as effective in multiprocessors as in traditional uniprocessors because they have failed to use all of the available information. In particular, these techniques typically rely only on the information available at run-time, which is insufficient in the complex environment of a multiprocessor system. The primary objective of this research project is to develop and analyze new techniques for improving multiprocessor memory performance by integrating hardware and software strategies to utilize all of the memory referencing information. The project will explore both semantic information at compile-time and dynamic information at run-time to improve data prefetching, processor scheduling, data placement, and cache coherence enforcement. The new techniques generated through this research will be validated using a unique combination of trace-driven simulations, mathematical models, software prototypes running on actual parallel machines, and implementation of new algorithms in a parallelizing compiler.