Multiprocessor Memory Design for High-Performance Computing

使计算机系统的数量急剧增加 解决“重大挑战”所需的性能 计算问题，将有必要纳入 更多的并行处理技术应用到新的计算机设计中。 一个主要的障碍，以实现高性能， 然而，多处理器是在以下情况下遇到的延迟 访问数据存储器。 目前用于减少 存储器延迟，例如数据预取、向量存储器 读取和私有数据缓存的效率 在多处理器中与在传统的单处理器中一样， 他们没有利用所有现有的信息。 在 特别地，这些技术通常仅依赖于 在运行时可用的信息，这是不够的， 多处理器系统的复杂环境。 的 该研究项目的主要目标是开发和 分析改进多处理器内存的新技术 通过集成硬件和软件策略， 利用所有的存储器引用信息。 的 项目将在编译时探索语义信息 以及运行时的动态信息， 预取、处理器调度、数据放置和缓存 一致性执行。 新技术产生于 这项研究将使用以下独特的组合进行验证： 轨迹驱动模拟，数学模型，软件 在实际的并行机器上运行的原型，以及 新算法在并行编译器中的实现。

To produce the dramatic increases in computer system performance needed to solve the "grand challenge" computational problems, it will be necessary to incorporate more parallel processing technology into new computer designs. A major impediment to achieving high performance in a multiprocessor, however, is the delay encountered when accessing the data memory. Current techniques for reducing the memory delay, such as data prefetching, vector memory fetches, and private data caches, have not been as effective in multiprocessors as in traditional uniprocessors because they have failed to use all of the available information. In particular, these techniques typically rely only on the information available at run-time, which is insufficient in the complex environment of a multiprocessor system. The primary objective of this research project is to develop and analyze new techniques for improving multiprocessor memory performance by integrating hardware and software strategies to utilize all of the memory referencing information. The project will explore both semantic information at compile-time and dynamic information at run-time to improve data prefetching, processor scheduling, data placement, and cache coherence enforcement. The new techniques generated through this research will be validated using a unique combination of trace-driven simulations, mathematical models, software prototypes running on actual parallel machines, and implementation of new algorithms in a parallelizing compiler.