Development of a Low-Power, RF Integrated Circuit R&D Infrastructure in Idaho for the Rapid Commercialization of Wireless, Personal Communication Consumer Products
Development of a Low-Power, RF Integrated Circuit R&D Infrastructure in Idaho for the Rapid Commercialization of Wireless, Personal Communication Consumer Products
批准号:
9977454
负责人:
Stephen Parke
金额:
$0.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-08-15 至 2002-07-31
中文摘要
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英文摘要
EPS 9977454ParkeIdaho is poised to become a major player in the next revolution in consumer electronics. Using the base of "Integrated Circuits" or "IC" companies already based in the state, together with the development of a more sophisticated low-power, RF Integrated Circuit research and development infrastructure as proposed in this activity, it can capture a share of the low-power, RF- Complementary Metal-Oxide-Silicon or CMOS communications market. By scaling CMOS transistors to lengths near a tenth of a micron, maximum switching frequencies exceeding 100GHz have recently been achieved. Because this high-performance can be achieved using a relatively low-cost manufacturing process, CMOS is rapidly becoming a serious option for many wireless Radio Frequency (RF) applications that were previously considered to be the exclusive domain of more expensive bipolar and gallium arsenide technologies. This new technology will allow for affordable, wireless personal communicators that can provide instant audio, video, and data communications from any location on Earth.In order for the cost advantage of RF-CMOS to be realized, it is critical that new ultra-low-power RF-CMOS transistors and circuits be developed. This project proposes to improve SPICE models needed for RF-CMOS devices, which will enable IC designers to have successful, first-pass designs of chips which operate in the GHz regime. It will also build and test a prototype single-chip, low power SOI RF-CMOS, CDMA spread-spectrum transceiver chip suitable for handheld applications. In 1997, Boise State opened a new Semiconductor Device Characterization Lab in which CMOS devices on 6-8' silicon wafers are electrically measured and modeled. This new equipment was obtained as part of a $2 million grant from Hewlett-Packard. In September 1998, Boise State also opened the new Idaho Microfabrication Laboratory, a Class 1000 cleanroom for both teaching and research, funded by the State. Together with an extensive CAD lab, these lab facilities will be used to accomplish the proposed research and to assist companies in commercializing the results.
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