ITR/AP: Modeling and Simulation of Sub-micron VLSI

对于下一代超大规模集成电路（VLSI），信号延迟将由互连的寄生电阻（R）、电容（C）和电感（L）主导。 快速、准确地提取RCL寄生参数对大规模集成电路的设计和验证至关重要。该项目将开发创新的算法和软件，用于快速准确地提取VLSI电路的RCL寄生。该项目的主要目标是设计预处理迭代方法来解决电感和电容提取问题中出现的线性系统。电感问题的求解器将使用一种新的螺线管基方法来隐式地预处理简化系统，从而使迭代方法快速收敛。快速近似的矩阵向量产品与密集系统matrices将使用有效的分层方法计算。算法中的并行性将被用来开发能够解决大型问题的高性能软件。 为该项目开发的软件将可移植到各种并行架构中。预计该代码将提供寄生RCL提取现实尺寸的深亚微米VLSI电路所需的性能。

For the next generation Very Large Scale Integration (VLSI) circuits, the signal delay will be dominated by parasitic resistance (R), capacitance (C), and inductance (L) of the interconnect. The ability to extract RCLparasitic quickly and accurately is crucial to the design and verification of large VLSI circuits. This project will develop innovative algorithms and software for fast and accurate extraction of RCL parasitic of VLSIcircuits. The main goal of the project is the design of preconditioned iterative methods for solving the linear systems arising in inductance and capacitance extraction problems. Solvers for the inductance problem willuse a novel solenoidal basis approach to precondition a reduced system implicitly, leading to rapid convergence of the iterative methods. Fast approximations to the matrix-vector products with dense system matriceswill be computed using efficient hierarchical methods. Parallelism in the algorithms will be exploited to develop high-performance software that is capable of tackling large problems. Software developed for this project will be portable across a variety ofparallel architectures. It is anticipated that the code will deliver the performance necessary for parasitic RCL extraction of deep sub-micron VLSI circuits of realistic sizes.