Chip-Package Co-Design Methodology for Integrated RF Microsystems

本研究的目的是利用片上系统和封装上的系统技术开发一种芯片封装协同设计方法。这是在集成射频微系统中跨越技术和电路的多个领域所必需的。这些系统包括射频、模拟和数字电路，并且对每个域对其他域和封装施加的约束很敏感。目前，大多数系统都是用cmos技术设计的，并受到数字领域需求的驱动。这项研究将分三个阶段进行。在这个项目的第一阶段，将调查射频电路性能的极限。还将研究数字物理设计环境对射频电路设计的限制。在第二阶段，将研究射频无源器件的新兴技术，如铜金属涂层和铁氧体材料沉积，并与标准的铝金属工艺进行比较。在第三阶段，将制定芯片和封装的联合设计方法，包括元件优化、布局规划和布线。开发的方法将在试验台上使用，该试验台将被制造和测试。RIT与佐治亚理工学院的合作带来了微系统科学和工程方面的专业知识，以及电子封装的设计、建模和表征。研究生和本科生将受益于研究合作的广度，包括芯片设计和封装的综合，以及集成射频微系统的进步

The research aims to develop a chip-package co-design methodology using System on a Chip and System on a Package technologies. This is necessary to span multiple domains both in technology and circuitry in integrated RF microsystems. These systems include RF, analog and digital circuits and are sensitive to the constraints imposed by each domain on the other domains and the package. Most systems are currently being designed in CMOS technology and are driven by the requirements of the digital domain. This research will be conducted in three phases. In the first phase of this project, limits of RF circuit performance will be investigated. The constraints of the digital physical design environment on Rf circuit design will also be examined. In the second phase, emerging technologies such as Copper metal layers and deposition of Ferrite material will be studied for RF passive components, and compared with standard Al metal technology. In the third phase, a co-design methodology will be developed for the chip and the package, that includes component optimization, floor planning and routing. The developed methodology will be used on a test bed that will be fabricated and tested. The RIT collaboration with Georgia Tech brings expertise in microsystems science and engineering together with design, modeling and characterization of electronic packaging. Graduate students and undergraduates will benefit from the breadth of the research collaboration that includes the synthesis of chip design and packaging, and the advances in integrated RF microsystems