Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Pipelined Data Converter Design Strategies for Sub-100nm Processes

混合信号电子技术研究：NSF 和 SRC 的联合倡议：100nm 以下工艺的流水线数据转换器设计策略

• 批准号: 0120345
• 负责人: Randall Geiger
• 金额: $ 15万
• 依托单位: Iowa State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-08-01 至 2004-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0120345&HistoricalAwards=false
• 关键词: Research; Mixed; Signal; Electronic; Technologies

Analog to Digital Converters (ADCs) are one of the key components that are needed in many integrated circuits today and the application and demand for the converters will only accelerate throughout the next decade as applications expand and the ability to put large systems on a chip becomes reality. Paralleling and enabling this growing demand is an evolution in semiconductor technology with processes that have a continued shrinking of feature sizes and supply voltages. Although these evolutions are providing dramatic speed and transistor density improvements in most digital circuits, they are presenting increasing challenges for realizing analog and mixed-signal functions and the two decade-old strategy of using the same basic circuit structures to implement key functional blocks such as the analog to digital converter will no longer be successful in the sub-100nm processes that are now under development.This research is focused on developing design methodologies that can be used to design high-performance analog to digital converters in sub-100nm semiconductor processes in which not only the supply voltages are decreasing but also the gain characteristics of the basic transistor are deteriorating. The three major initiatives in the project are a) developing techniques for building fast high-gain operational amplifiers that can operate with very low supply voltages, b) developing built-in self-calibration and built-in self-test algorithms for pipelined data converters, and c) incorporating these results into a prototype converter than will be fabricated in a fine resolution process so that the theoretical performance characteristics can be experimentally validated.The low voltage operational amplifiers should find applications in sub-100nmprocesses well beyond their use in pipelined data converters. The self-calibration strategy is based upon treating the pipelined data converter as a system, which is identified through the use of a dedicated digital signal processing block. This approach will provide for yield enhancement and will inherently provide capability for built-in self-test which will be of increasing importance as increasingly complex analog and mixed-signal functions become deeply embedded in large single-chip systems.

模数转换器（ADC）是当今许多集成电路中所需的关键组件之一，随着应用的扩展以及将大型系统集成到芯片上的能力成为现实，在未来十年中，对转换器的应用和需求只会加速。满足和实现这种不断增长的需求是半导体技术的发展，其工艺具有持续缩小的特征尺寸和电源电压。尽管这些发展在大多数数字电路中提供了惊人的速度和晶体管密度改进，它们对实现模拟和混合信号功能提出了越来越多的挑战，并且使用相同的基本电路结构来实现诸如模数转换器之类的关键功能块的二十年前的策略将不再成功。本研究的重点是开发可用于设计亚微米级高性能模数转换器的设计方法。100nm半导体工艺，其中不仅电源电压降低，而且基本晶体管的增益特性也恶化。该项目的三个主要举措是：a）开发用于构建可以在非常低的电源电压下工作的快速高增益运算放大器的技术，B）开发用于流水线数据转换器的内置自校准和内置自测试算法，以及c）将这些结果结合到将在精细分辨率工艺中制造的原型转换器中，使得可以低压运算放大器在亚100 nm工艺中的应用远远超出了它们在流水线数据转换器中的应用。自校准策略基于将流水线数据转换器视为一个系统，该系统通过使用专用数字信号处理块来识别。这种方法将提供成品率的提高，并将固有地提供内建自测试的能力，这将随着越来越复杂的模拟和混合信号功能深深地嵌入到大型单芯片系统中而变得越来越重要。