CAREER: DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOS

职业：亚微米 CMOS 中的 DSP 增强型低压信号处理

• 批准号: 0133530
• 负责人: Un-Ku Moon
• 金额: $ 35万
• 依托单位: Oregon State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-07-01 至 2007-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0133530&HistoricalAwards=false
• 关键词: CAREER; DSP; Enhanced; Low; Voltage

DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOSToday's electronic systems are strongly influenced by the dramatic advancement of submicron complementary metal-oxide-silicon (CMOS) integrated circuits (IC) technology as the size of transistors shrink to extreme dimensions. Because of the shrinking size of transistors, the digital signal processing (DSP) power and efficiency of digital computation grow exponentially; however, the equally decreasing operating voltage of the transistors leads to design problems for mixed analog-digital circuits which are part of all digital processors. By taking advantage of the CMOS down-scaling trend that increases DSP capability, this research combines the developmental efforts in both low-voltage analog circuit techniques and optimum architectures for DSP enhancements. This research systematically explores various architectures, develops and comparesadaptive algorithms and digital correction techniques, studies the effects of analog imperfections in deep submicron CMOS, and obtains the fundamental limits of digital compensation and calibration.In this research, two IC design methods are created and expanded to overcome the analog/mixed-signal design challenges of very deep submicron CMOS technologies. The first explores new architectures and techniques capable of maximizing the power of DSP for enhancing analog and mixed-signal circuit performance, including DSP-enabling architectures, use of multi-signal paths and taking advantage of inherent structures for error estimation, and merged system calibration of multi-stage architectures. The second explores new analog circuit design techniques for ultra low-voltage operation that is fully compatible with submicron CMOS, focusing on fast low-voltage switching schemes, analog-error insensitive and DSP-corrected low-voltage structures, and linear low-voltage input sampling circuits.

亚微米CMOS中DSP增强的低压信号处理随着晶体管尺寸缩小到极限尺寸，亚微米互补金属氧化物硅（CMOS）集成电路（IC）技术的巨大进步对当今的电子系统产生了巨大影响。由于晶体管尺寸的缩小，数字信号处理（DSP）的功率和数字计算的效率呈指数增长;然而，晶体管的工作电压的同等降低导致作为所有数字处理器的一部分的混合模数电路的设计问题。通过利用CMOS缩小规模的趋势，提高DSP的能力，本研究结合了低电压模拟电路技术和DSP增强的最佳架构的发展努力。本研究系统地探讨了各种结构，发展和比较了自适应算法和数字校正技术，研究了深亚微米CMOS工艺中模拟缺陷的影响，得出了数字补偿和校准的基本限制，并提出和扩展了两种集成电路设计方法，以克服非常深亚微米CMOS工艺中模拟/混合信号设计的挑战。第一个探索新的架构和技术，能够最大限度地提高模拟和混合信号电路的性能，包括DSP使能架构，多信号路径的使用和利用固有的结构进行误差估计，并合并系统校准的多级架构的功率DSP。第二个探索新的模拟电路设计技术，超低电压操作，是完全兼容的亚微米CMOS，专注于快速低电压开关方案，模拟误差不敏感和DSP校正的低电压结构，和线性低电压输入采样电路。