CAREER: DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOS

如今的电子系统受到亚微米互补金属氧化物硅（CMOS）集成电路（IC）技术的巨大进步的强烈影响，因为晶体管的尺寸缩小到极限尺寸。由于晶体管尺寸的不断缩小，数字信号处理（DSP）的功率和数字计算效率呈指数级增长；然而，晶体管工作电压的同样下降导致了所有数字处理器组成部分的混合模拟-数字电路的设计问题。通过利用CMOS的缩小趋势，增加DSP的能力，本研究结合了低压模拟电路技术和DSP增强的最佳架构的发展努力。本研究系统地探索了各种结构，开发和比较了自适应算法和数字校正技术，研究了深亚微米CMOS中模拟缺陷的影响，并得出了数字补偿和校准的基本极限。在本研究中，创建并扩展了两种IC设计方法，以克服极深亚微米CMOS技术的模拟/混合信号设计挑战。第一部分探讨了能够最大化DSP功能以增强模拟和混合信号电路性能的新架构和技术，包括DSP支持架构，使用多信号路径并利用固有结构进行误差估计，以及多级架构的合并系统校准。第二部分探讨了与亚微米CMOS完全兼容的超低电压操作的新型模拟电路设计技术，重点研究了快速低压开关方案、模拟误差不敏感和dsp校正的低压结构以及线性低压输入采样电路。

DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOSToday's electronic systems are strongly influenced by the dramatic advancement of submicron complementary metal-oxide-silicon (CMOS) integrated circuits (IC) technology as the size of transistors shrink to extreme dimensions. Because of the shrinking size of transistors, the digital signal processing (DSP) power and efficiency of digital computation grow exponentially; however, the equally decreasing operating voltage of the transistors leads to design problems for mixed analog-digital circuits which are part of all digital processors. By taking advantage of the CMOS down-scaling trend that increases DSP capability, this research combines the developmental efforts in both low-voltage analog circuit techniques and optimum architectures for DSP enhancements. This research systematically explores various architectures, develops and comparesadaptive algorithms and digital correction techniques, studies the effects of analog imperfections in deep submicron CMOS, and obtains the fundamental limits of digital compensation and calibration.In this research, two IC design methods are created and expanded to overcome the analog/mixed-signal design challenges of very deep submicron CMOS technologies. The first explores new architectures and techniques capable of maximizing the power of DSP for enhancing analog and mixed-signal circuit performance, including DSP-enabling architectures, use of multi-signal paths and taking advantage of inherent structures for error estimation, and merged system calibration of multi-stage architectures. The second explores new analog circuit design techniques for ultra low-voltage operation that is fully compatible with submicron CMOS, focusing on fast low-voltage switching schemes, analog-error insensitive and DSP-corrected low-voltage structures, and linear low-voltage input sampling circuits.