Scalable and Synthesizable Analog Circuits for Nanometer CMOS

用于纳米 CMOS 的可扩展和可合成模拟电路

• 批准号: 1128715
• 负责人: Un-Ku Moon
• 金额: $ 36万
• 依托单位: Oregon State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1128715&HistoricalAwards=false
• 关键词: Scalable; Synthesizable; Analog; Circuits; Nanometer

ECCS-1128715PI: Un-Ku Moon Institution: Oregon State UniversityTitle: Scalable and Synthesizable Analog Circuits for Nanometer CMOSABSTRACTIntellectual Merit: Analog-to-digital converters are a mixture of analog circuits and digital blocks. The analog portion of such analog-intensive blocks requires careful design, layout, and are often the main source of power consumption and chip area. The objective of this research is to develop such analog-intensive blocks with all digital cells and automatically generate the final chip design and layout using digital synthesis tools such as Verilog. Instead of combating the challenges brought forth by the new nanometer processes, this work seeks to analyze and take advantage of these non-ideal effects. Problems such as increased offset and reduced intrinsic gain of the minimum size transistor will be addressed, and new approaches at both system and circuit levels will be explored to overcome these issues. Different structures such as stochastic analog-to-digital converter and oversampling delta-sigma modulator will be explored. Semi-analog blocks such as inverter-based integrator that would either be synthesized via existing synthesis tool (e.g. Verilog) or newly developed automatic synthesis tools will be explored. By synthesizing semi-analog and digital blocks, the proposed research will further enable highly integrated analog-intensive blocks for the next generation nanometer processes. Proficient high level modeling of blocks via synthesis tools allows fast simulation and verification, and effortless migration to another process, alleviating the typical brute-force redesigning tasks required in traditional analog-intensive blocks. A readily available synthesized digital signal processing system is also expected to further enhance the performance of these new synthesizable analog functioning digital structures.Broader Impacts: The design methodology that will emerge from this research merges both the analog and digital functionality in the automatic synthesis of a system from a software program to an integrated circuit realization. Such combined optimization of analog and digital signal processing, as incorporated into undergraduate and graduate education, will reshape the way students approach chip design challenges. Such foundation will provide and push students to seek solutions from a much wider perspective before making the final design decisions. This training will lead to well-rounded and innovative future engineers who are well versed in both digital and analog aspects of chip design. The research results to be disseminated in prestigious journals and conferences will expose and educate the public at large and further motivate these new concepts to be investigated by other researchers. Also, the enabling ideas explored in this proposal will directly affect most portable and stationary systems, which are important segments of the microelectronics market today. The ability to automatically synthesize data converters with all-digital blocks may allow the use of these structures in digital processors, medical and bio-medical integrated circuits, and other important systems utilizing analog-to-digital interface and digital signal processing, significantly lowering the cost of integrated circuit systems.

ECCS-1128715 PI：Un-Ku Moon机构：俄勒冈州州立大学标题：用于纳米CMOS的可扩展和可合成模拟电路BSTRACT智力优势：模数转换器是模拟电路和数字模块的混合体。这种模拟密集型模块的模拟部分需要仔细设计和布局，并且通常是功耗和芯片面积的主要来源。本研究的目的是开发这样的模拟密集型块与所有数字单元，并自动生成最终的芯片设计和布局使用数字合成工具，如Verilog。这项工作不是应对新纳米工艺带来的挑战，而是试图分析和利用这些非理想的效果。诸如最小尺寸晶体管的失调增加和固有增益降低等问题将得到解决，并将探索在系统和电路两级的新方法来克服这些问题。不同的结构，如随机模数转换器和过采样delta-sigma调制器将被探讨。半模拟模块，如基于逆变器的积分器，将通过现有的合成工具（如Verilog）或新开发的自动合成工具进行合成将被探索。通过合成半模拟和数字模块，拟议的研究将进一步为下一代纳米工艺提供高度集成的模拟密集型模块。通过综合工具对模块进行熟练的高级建模，可以快速仿真和验证，并轻松迁移到另一个流程，从而减轻传统模拟密集型模块所需的典型蛮力重新设计任务。一个现成的合成数字信号处理系统也有望进一步提高这些新的合成模拟功能的数字structure.Broader影响的性能：设计方法，将出现从这项研究合并的模拟和数字功能的自动合成系统从软件程序到集成电路实现。这种模拟和数字信号处理的组合优化，作为纳入本科和研究生教育，将重塑学生的方法芯片设计的挑战。这样的基础将提供并推动学生在做出最终设计决定之前从更广泛的角度寻求解决方案。这项培训将培养出精通芯片设计的数字和模拟方面的全面且具有创新精神的未来工程师。将在著名期刊和会议上传播的研究结果将使广大公众了解和接受教育，并进一步激励其他研究人员对这些新概念进行研究。此外，本提案中探讨的使能思想将直接影响大多数便携式和固定式系统，这些系统是当今微电子市场的重要部分。自动合成具有全数字块的数据转换器的能力可以允许在数字处理器、医学和生物医学集成电路以及利用模数接口和数字信号处理的其他重要系统中使用这些结构，从而显著降低集成电路系统的成本。