SGER: Exploring Massive Chip Level Active Deskewing for VLSI Chips Beyond 20GHz

在过去的几十年里，VLSI芯片的时钟频率和集成度已经达到了一个水平，分配时钟已经成为一项越来越困难的任务。最新发布的芯片运行速度超过2 GHz-时钟速率。未来5-10年，ULSI芯片的性能预测将高达20 GHz。这意味着整个芯片的总时钟偏差需要保持在5ps以下，以便将时钟偏差的量控制在总时钟周期的10%以内。超过50纳米代的未来加工技术中工艺差异的急剧增加将进一步加剧这一问题。此外，当芯片包含越来越多的元件(门)时，芯片上开关活动的差异将会变化得更大，从而导致温度和电源噪声在芯片上的变化更大，这是时变的。这里提出的研究旨在探索一种截然不同的设计范例，用于设计和分配未来的时钟信号，其中时钟网络将动态适应芯片的操作环境，以实时执行抗偏斜功能。有源去偏斜使用片上有源器件，例如延迟锁定环路(DLL)来检测和减少芯片上任意两点之间的偏斜。建议的研究解决的问题包括：给定芯片体系结构和芯片上使用的块的特性(开关、泄漏和密度)，必须稳定的自调整去偏斜网络的最佳拓扑是什么？考虑到芯片的性能要求，芯片可以容忍的去偏斜网络的最大延迟是多少？去偏斜电路的分辨率是多少？这对时钟网络的整体性能有何影响？研究包括广泛的理论探索，以确定这种去偏斜方法的实用性。整个减斜系统的数学模型被表示为一个多输入、多输出(MIMO)离散时间动态系统。基于该模型的稳定性分析正在进行中。这种方法利用了鲁棒控制理论的结果，即使对摄动系统也能保证稳定性。

During the last several decades, the clock rate and the level of integration of VLSI chips have reached a level that distributing clocks has become an increasingly difficult task. The most recently released chips run at more than 2GHz-clock rate. The performance projection for future ULSI chips will be up to 20GHz in the next 5-10 years. This implies that the overall clock skew needs to be kept under 5ps across the chip in order to control the amount of clock skew to be within 10% of the total clock cycle. This problem will be further exacerbated by the steep increase in process variations in future processing technologies beyond 50nm generations. Furthermore, when chips contain more and more components (gates), the disparity of switching activities on chip will vary more widely resulting in greater on-chip variations of temperature and supply noise, which are time-variant. The research proposed here is intended to explore a dramatically different design paradigm for designing and distributing clock signals for the future where the clocking networks will be dynamically adapted to chip's operating environment to perform a deskewing function in real-time. Active deskewing uses on-chip active devices such as delay-locked loops (DLLs) to detect and reduce skews between any two points on the chip. The issues the proposed research addresses include: Given a chip architecture and the characteristics (switching, leakage, and density) of the blocks used on the chip, what is the optimal topology of the self-adjusting deskewing network that must be stable?Given the performance requirements for the chip, what is the maximum latency of the deskewing network the chip can tolerate?What is the resolution of deskewing circuits? And how does this affect the overall performance of the clock network?Research includes an extensive exploration theoretically to determine the practicality of such a deskewing approach. A mathematical model for the entire deskewing system is formulated as a multi-input, multi-output (MIMO) discrete-time dynamic system. A stability analysis based upon the model is being developed. This approach uses results from robust control theory that can guarantee stability even for perturbed systems.