GOALI: A Truly CMOS Compliant On-Chip Optical Interconnect System for VLSI Chips

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The research program proposed here is designed to demonstrate a purely on-chip, multi-GHz, optical interconnect system implemented in deep submicron CMOS technology from commercial silicon foundries. The critical governing philosophy is to strictly limit the optical interconnect component technology wherever possible to materials and processes found in conventional state- of-the-art integrated circuits. In an effort to address electrical interconnect issues, CMOS materials technology has expanded to include low-k dielectrics, new metallurgy, and copper encapsulation films. We propose to use these very tools to implement optical interconnects. Specifically, the optical interconnect will be based on waveguides composed of silicon nitride and low-k dielectrics already present as CMOS interconnect dielectric layers and Schottky barrier contacted polysilicon photodiodes made from standard CMOS resistor polysilicon films. The use of polysilicon photodetectors rather than crystalline photodetectors allows us to move the photodetectors out of the noisy substrate environment that is typical in high performance digital VLSI chips to less noisy and more well controlled back-end layers. Preliminary work has been performed in our laboratory on MSM photodiodes based on amorphous silicon. The increased performance of the MOSFETs themselves will be leveraged to implement multi-GHz receivers. The only component that cannot be implemented in CMOS is a high speed, high power optical source for which a single edge emitting laser diode will be used. All CMOS related wafer manufacturing will be provided by our industrial partner, Agilent Technologies. In addition, Agilent Technologies, with their extensive expertise in ASIC and optical IC designs, will also collaborate with us to evaluate concepts and improve designs. This unique relationship is a key to ensure the practicality of the proposed technology. Therefore, the intellectual merit of the proposed research lies in the method that makes exclusive use of materials and processing steps in modern silicon CMOS technologies to embed on-chip optical interconnect structures. This is, to our best knowledge, the first attempt to develop, design, and demonstrate a complete integrative system that will provide valuable data for further advances in silicon technology.The impact of the proposed research is threefold. Firstly, it provides necessary impetus for technology advances along the Moore's Law well beyond the path that is projected by ITRS. The proposed research is aimed at solutions that can become one of the enabling technologies for the next 5-10 years. Secondly, it provides a well-balanced forum for academic and industrial collaboration and participation. Such close collaboration ensures practicality of potential technologies. Furthermore, research results can be disseminated faster and more convincingly through our industrial partners in addition to regular publication channels. Lastly, the Rocky Mountain region has a high concentration of R&D facilities in semiconductor and optical engineering. Cross-pollinations between these two disciplines are crucial for incubating new technologies.The proposed research will allow us to create cross-disciplinary curriculum and seminar. We also propose to organize a first international workshop on fully CMOS compliant on-chip optical interconnects to assemble researchers in this field to further exchange ideas and discuss issues. Using our research results, we will offer tutorials at other related conferences, such as ISCAS and ICCC. Furthermore, we will bring a high-school science teacher into the project to create a "Science Fair" project in a local high school. The project will be involved with up to 4 high school students participating in debugging and measurement wave guide materials. The students will compete in Colorado Science Fair competition using the results from the project.