ITR: Enabling Novel Digital Sequential Circuit Designs through Error Control and Noise Tolerance Techniques

ITR：通过错误控制和噪声容限技术实现新型数字时序电路设计

• 批准号: 0218939
• 负责人: Christoforos Hadjicostis
• 金额: $ 24万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-08-15 至 2006-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0218939&HistoricalAwards=false
• 关键词: ITR; Enabling; Novel; Digital; Sequential

The proposed research aims at extending the benefits of scaling (i.e., Moore's Law) into the ub-0.07$\mu$m regime by developing error control techniques for digital sequential circuits. The overall goal is to evaluate the practical implications of recently developed dynamic error correction and algorithmic noise tolerance techniques in terms of enabling the design of sequential circuit architectures that are cost-effective and operate at speed and energy efficiencies that exceed the limits imposed by current VLSI architectures. Thesuccessful completion of this project can lead to the development of acomprehensive set of circuit design techniques that permit tradeoffs between reliability, speed and energy-efficiency in ways that have notbeen exploited before. The objectives of this research thrust are two-fold: (i) The immediate goal is to develop error control methodologies that enable the construction of functional sequential systems out of unreliable components that may be fast, inexpensive or have reduced energy requirements. The novelty of the proposed research lies in that it it explores the case when the error correction mechanism operates at a different time scale than the rest of the system. (ii) The ultimate goal is to build prototypes of such sequential circuits in order toevaluate their actual performance and potential. The proposed research also has a significant educational and outreachcomponent, motivating graduate students to contribute to research thatfocuses on the fringes of circuit theory, signal processing, codingand graph theory, control theory and information theory.

拟议的研究旨在扩大规模化的好处（即，摩尔定律）进入ub-0.07\mu $m制度，通过开发数字时序电路的错误控制技术。 总体目标是评估最近开发的动态纠错和算法噪声容限技术的实际影响，使时序电路架构的设计，具有成本效益和运行速度和能源效率，超过目前的VLSI架构所施加的限制。 这个项目的成功完成可以导致一套完整的电路设计技术的发展，允许可靠性，速度和能源效率之间的权衡，以前没有被利用的方式。这项研究的目标有两个方面：（一）直接目标是开发错误控制方法，使不可靠的组件，可能是快速，廉价或减少能源需求的功能顺序系统的建设。 所提出的研究的新奇在于，它探讨了纠错机制在与系统其他部分不同的时间尺度上运行的情况。 (ii)最终的目标是建立这种时序电路的原型，以评估其实际性能和潜力。拟议中的研究也有一个重要的教育和外展组成部分，激励研究生致力于研究，重点是电路理论，信号处理，编码和图论，控制理论和信息理论的边缘。