NIRT: Spatially Ordered Self-Assembled Quantum Dot Gate Low Voltage/Power, High Speed Nanoscale Flash Memories

该NIRT提案侧重于高速，低功耗，高密度Si-Ge-C平面和垂直闪存电可擦除和可编程只读存储器（eeprom）的技术和基础科学，该存储器使用高k电介质和Si-Ge-C或金属自组装量子点（SAQD）浮动门。传统的闪存eeprom有几个严重的缺点，本研究旨在研究新的存储单元结构，为未来的集成电路设备提供紧凑、低功耗、高速（编程、擦除和读取操作）的半导体存储技术。本研究将从实验和理论两方面探索：(1)利用化学/物理气相沉积（CVD或PVD）技术，在介电表面生长有序的Si-Ge-C和金属纳米颗粒阵列。我们将尝试实现高密度，空间控制和窄粒度分布，与压印光刻技术相一致；(2)开发高基快闪存储器，允许物理上更厚，但电上更薄的“等效”氧化物；(3)利用低带隙、高迁移率的Si-Ge-C异质层作为“冷阴极”；(4)垂直纳米级闪存eeprom，这将允许沿通道使用Si-Ge-C进行带隙工程；5)纳米颗粒结构演化的第一性原理建模，包括成核、生长、结晶和介电内的包封，以支持实验生长研究；6)热载流子输运的流体力学和蒙特卡罗模拟理论建模，隧道输运的传递矩阵方法，以及SAQDs中库仑封锁效应的量子输运计算。saqd增强电荷保持和VT稳定性，并可能基于库仑封锁实现多级存储。高基介电材料应在不牺牲非挥发性的情况下提供高电容耦合，并通过降低通道热电子（CHE）注入和隧穿的势垒高度来实现更低的电压和/或更高的速度，并由于在低场存储条件下更厚的隧穿势垒而增加器件寿命。Si-Ge-C平面闪光电池应增强冲击电离和CHE，以降低工作电压/功率和提高编程速度。垂直单元结构将允许在所谓的交叉点架构中实现最高的密度，其中单元位于字线和位线的交叉点。研究的合作性质将提高研究生的经验和发展团队建设技能。这四名研究生将受益于四名合作pi的联合监督。通过这些经历，他们将更多地了解自己专业以外的领域，并了解其他学科如何定义问题和解决问题的方法。他们还将有机会指导本科生，并让他们对尖端纳米技术研究感到兴奋。为了给普通大众和大学预科学生带来纳米级物体和设备的兴奋感，共同研究人员和他们的学生将开发、生产和展示展品，解释这些革命性的设备及其制造过程。展品将用于当地和区域科学趣味日和博览会；在区域K-12学校和博物馆展出；并用于巡回展览拖车，将工程意识带到德克萨斯州代表性不足的选区。我们将与摩托罗拉奥斯汀“先进材料和记忆”经理Bruce White博士建立紧密的产业联系。

This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.