NIRT: Spatially Ordered Self-Assembled Quantum Dot Gate Low Voltage/Power, High Speed Nanoscale Flash Memories

NIRT：空间有序自组装量子点门低电压/功耗高速纳米级闪存

• 批准号: 0304026
• 负责人: Sanjay Banerjee
• 金额: --
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-15 至 2008-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0304026&HistoricalAwards=false
• 关键词: NIRT; Spatially; Ordered; Self; Assembled

This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.

该NIRT提案的重点是技术和基础科学，用于高速，低功率，高密度的SI-GE-C平面和垂直闪光灯电气可擦除和可编程的读取记忆（EEPROM），并使用High-k Dielectrics和SI-GE-C或金属自组装量子点（SAQD）浮球段。传统的闪光EEPROM具有几个严重的缺点，这项研究研究了新的记忆细胞结构，目的是为未来的集成电路设备提供紧凑，低功率，高速（编程，擦除和读取操作）半导体内存技术。这项研究将在实验和理论上探索：（1）使用化学/物理蒸气沉积（CVD或PVD）技术，SI-GE-C和金属纳米颗粒有序的阵列在介电表面上的生长，这些技术是从生长中取消成核的。 我们将尝试与烙印光刻技术一起实现高密度，空间控制和狭窄的粒度分布。 （2）开发基于高K的闪存，以使物理上较厚，但具有较薄的“等效”氧化物； （3）在平面闪光细胞通道中的低频带间隙，高迁移率SI-GE-C异层，充当“冷阴极”； （4）垂直纳米级闪光EEPROM，它将允许使用沿通道的SI-GE-C进行带隙工程； 5）纳米颗粒结构演化的第一原理建模，包括介电内的成核，生长，结晶和封装，以支持实验生长研究； 6）通过流体动力和蒙特卡洛模拟，使用转移矩阵方法进行隧穿的热载体传输的理论建模，以及SAQD中库仑封锁效应的量子传输计算。 SAQDS增强了电荷保留和VT稳定性，并可能允许基于库仑封锁的多级存储。 高基于高的电介质应提供高电容耦合，而不会牺牲非挥发性，并通过在低场储存条件下的较厚的隧道式障碍，因此通过势垒高度（CHE）注入和/或更高速度的操作，从而通过屏障高度减少到通道热电子（CHE）注射和隧道渠道，并增加了设备寿命。 SI-GE-C平面闪存电池应增强影响电离和CHE，以降低工作电压/功率并提高编程速度。 垂直单元结构将允许在所谓的交叉点体系结构中允许最高的密度，其中该单元格位于单词线和位线的交叉点上。研究的协作性质将增强研究生的体验并发展团队建设技能。 四个研究生将受益于四个共同私募派的联合监督。 通过这一经验，他们将进一步了解主要研究领域以外的领域，并对其他学科如何定义问题和解决他们的解决方案表示赞赏。他们还将有机会指导下级学生，并使他们对尖端的纳米技术研究感到兴奋。为了将纳米级对象和设备的兴奋带给公众和预科学生，共同投资者及其学生将开发，制作和展示展览品，以解释这些革命性的设备及其捏造。 展览将是：在本地和地区科学娱乐日和博览会上使用；可在区域K-12学校和博物馆展出；并在巡回展览预告片中使用，该预告片将工程意识带到了德克萨斯州代表性不足的选区。我们将与奥斯丁摩托罗拉的“高级材料和回忆”经理布鲁斯·怀特（Bruce White）博士建立牢固的工业联系。