NIRT: Spatially Ordered Self-Assembled Quantum Dot Gate Low Voltage/Power, High Speed Nanoscale Flash Memories

NIRT：空间有序自组装量子点门低电压/功耗高速纳米级闪存

• 批准号: 0304026
• 负责人: Sanjay Banerjee
• 金额: --
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-15 至 2008-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0304026&HistoricalAwards=false
• 关键词: NIRT; Spatially; Ordered; Self; Assembled

This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.

该NIRT提案侧重于使用高k MOSFET和Si-Ge-C或金属自组装量子点（SAQD）浮栅的高速、低功耗、高密度Si-Ge-C平面和垂直闪存电可擦除和可编程只读存储器（EEPROM）的技术和基础科学。传统的闪存EEPROM有几个严重的缺点，本研究调查新的存储单元结构的目标是提供一个紧凑，低功耗，高速（编程，擦除和读取操作）的半导体存储器技术，为未来的集成电路器件。本研究将从实验和理论上探讨：（1）利用化学/物理气相沉积（CVD或PVD）技术在电介质表面上生长Si-Ge-C和金属纳米颗粒的有序阵列，使成核与生长解耦。 我们将努力实现高密度、空间控制和窄的颗粒尺寸分布，与压印光刻技术相协调;（2）开发基于高k的闪存，以允许物理上更厚但电学上更薄的“等效”氧化物;（3）在平面闪存单元的沟道中的低带隙、高迁移率Si-Ge-C异质层，以充当“冷阴极”;（4）垂直纳米级快闪EEPROM，这将允许沿着沟道使用Si-Ge-C进行带隙工程; 5）纳米颗粒结构演变的第一性原理建模，包括电介质内的成核、生长、结晶和封装，以支持实验生长研究; 6）流体动力学和MonteCarlo模拟热载流子输运的理论模型，传输矩阵方法的隧穿输运，以及SAQD中库仑阻塞效应的量子输运计算。 SAQD增强电荷保持和VT稳定性，以及可能允许基于库仑阻塞的多级存储。 基于高k的MOSFET应该提供高电容耦合，而不牺牲非易失性，并且通过沟道热电子（CHE）注入和隧穿的势垒高度的潜在降低以及由于在低场存储条件下较厚的隧穿势垒而增加的器件寿命来允许较低电压和/或较高速度的操作。 Si-Ge-C平面闪存单元应增强碰撞电离和CHE，以降低操作电压/功率并提高编程速度。 垂直单元结构将允许所谓的交叉点架构中的最高可能密度，其中单元位于交叉点和交叉点的交叉点处。研究的协作性质将提高研究生的经验和发展团队建设技能。 这四名研究生将受益于四个合作PI的联合监督。 通过这种经验，他们将更多地了解他们的主要研究领域之外的领域，并获得其他学科如何定义问题和解决方案的赞赏。他们还将有机会指导本科生，让他们对尖端的纳米技术研究感到兴奋。为了给公众和大学预科生带来纳米级物体和设备的兴奋，合作研究人员和他们的学生将开发，制作和展示解释这些革命性设备及其制造的展品。 展品包括：在当地和区域科学有趣的日子和博览会上使用;在区域K-12学校和博物馆展出;并在旅行展览拖车中使用，为德克萨斯州代表性不足的选区带来工程意识。我们将与奥斯汀摩托罗拉公司“先进材料和存储器”经理布鲁斯白色博士建立强有力的工业联系。