NIRT: Spatially Ordered Self-Assembled Quantum Dot Gate Low Voltage/Power, High Speed Nanoscale Flash Memories

这项NIRT计划侧重于高速、低功耗、高密度的Si-Ge-C平面和垂直闪存电可擦除和可编程只读存储器(EEPROM)的技术和基础科学，该存储器使用High-k介质和Si-Ge-C或金属自组装量子点(SAQD)浮动栅极。传统的闪存EEPROM有几个严重的缺陷，本研究调查了新的存储单元结构，目的是为未来的集成电路器件提供紧凑、低功耗、高速(编程、擦除和读取操作)的半导体存储技术。本研究将从实验和理论上探索：(1)利用化学/物理气相沉积(CVD或PVD)技术分离成核和生长，在介质表面生长有序的Si-Ge-C和金属纳米颗粒阵列。我们将努力实现高密度、空间控制和窄颗粒尺寸分布，与压印光刻技术相配合；(2)开发基于High-k的闪存，以实现物理上更厚、但电上更薄的“等效”氧化物；(3)在平面闪存单元的沟道中使用低带隙、高迁移率的Si-Ge-C异质层作为“冷阴极”；(4)垂直纳米级闪存EEPROM，它将允许沿沟道使用Si-Ge-C进行带隙工程；5)纳米粒子结构演化的第一性原理模拟，包括电介质中的成核、生长、结晶和封装，以支持实验生长研究；6)通过流体力学和蒙特卡罗模拟对热载流子输运进行理论模拟，利用转移矩阵方法进行隧道输运，以及库仑阻塞效应在SAQD中的量子输运计算。SAQD增强了电荷保持和VT稳定性，并可能允许基于库仑阻塞的多级存储。高k基电介质应在不牺牲非易失性的情况下提供高电容耦合，并通过降低沟道热电子(CHE)注入和隧穿的势垒高度来实现较低电压和/或更高速度的操作，并由于低场存储条件下较厚的隧穿势垒而延长器件寿命。Si-Ge-C平面闪存单元应增强碰撞电离和CHE，以降低操作电压/功率并提高编程速度。垂直单元结构将允许在所谓的交叉点架构中实现最高密度，其中单元位于字线和位线的交叉处。研究的协作性将增强研究生的体验并培养团队建设技能。四名研究生将受惠于四名协理督导的联合督导。通过这次经历，他们将更多地了解其主要研究领域以外的领域，并了解其他学科是如何定义问题和解决问题的。他们还将有机会指导本科生，让他们对尖端的纳米技术研究感到兴奋。为了给普通公众和预科学生带来纳米级物体和设备的兴奋，合作研究人员和他们的学生将开发、制作和展示解释这些革命性设备及其制造的展品。这些展品将用于当地和地区的科学游乐日和博览会；在地区的K-12学校和博物馆展出；并用于巡回展览预告片，将工程意识带给德克萨斯州代表不足的选区。我们将与奥斯汀摩托罗拉“先进材料和存储器”经理布鲁斯·怀特博士建立强大的行业联系。

This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.