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Collaborative Research: Defect Immune, Topologically Protected Devices for Ultra-Low Power Electronics

Collaborative Research: Defect Immune, Topologically Protected Devices for Ultra-Low Power Electronics
合作研究:用于超低功率电子器件的缺陷免疫、拓扑保护器件
批准号:
1802167
负责人:
Sanjay Banerjee
金额:
$12.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-08-01 至 2021-07-31

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中文摘要
翻译
材料的缺陷,如缺陷或边缘粗糙,常常严重限制电子设备的性能。这在纳米尺度上尤其成问题,因为即使是单个原子缺陷也会严重破坏传输。因此,能够容忍这些缺陷的设备是未来技术的关键。研究人员提出了两种新的耐缺陷器件概念的基本特性和集成,通过新型2D和3D拓扑绝缘体(ti)实现,这些绝缘体具有前所未有的低功耗,室温性能和功能,只有使用这些独特的材料才能实现。这种对缺陷的容忍度将使纳米电子学超越目前已知的极限,并将特别影响超低功耗、后硅电子技术的国家重大挑战,并代表着国家技术力量半导体电子领域的重大进步。一组具有互补专业知识的研究人员,包括由有成就的高级教授补充的初级研究人员,将解决拟议工作的挑战。这项研究还将扩大科学和教育的参与,通过例如nsf资助的本科生研究经验(REU)项目和与国家实验室和行业合作伙伴的合作,创造一个大学预科和本科生学习科学和工程的渠道。研究人员还将通过科学咖啡馆项目吸引公众,教师们将在当地的酒吧和餐馆展示他们的研究成果。这个合作研究团队将阐明基于拓扑绝缘体(TI)的纳米电子器件概念的基础科学和技术含义,这些器件可以在低功耗、远高于室温的条件下工作。两个互补的研究方向将继续进行,这两个方向都将实现一种新型的、超低功耗的、拓扑保护的铋基材料器件:1)基于二维ti的场效应晶体管,它不受材料和器件缺陷(如缺陷和线边缘粗糙度)的影响;2)基于三维ti的隧道器件,利用自旋滤波表现出负差分电阻,具有前所未有的峰谷比性能。通过分子束外延(Hinkle)生长TI将重点放在2D Bi和3D Bi2Se3上,这预示着室温器件的应用。表面和边缘状态检测以及化学/结构特性将使用原位技术进行研究(Wallace)。理论研究包括密度泛函理论(DFT),散射和迁移率计算(范登伯格)将被采用。先进的2端和3端器件将被制造(Banerjee),这些器件的特性将在NAND门中进行评估。这项研究将为先进的低功耗,高性能逻辑,存储器,甚至使用ti的振荡神经形态应用提供材料和器件概念,ti是一类对缺陷/杂质非常强大的器件。通过与NIST合作,还将建立TI和2D材料属性和基准数据库。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Imperfections in materials, such as defects or edge roughness, often severely limit electronic device performance. This is especially problematic at the nanoscale where even a single atomic defect can drastically disrupt transport. Devices that are tolerant to these imperfections are thus the key to future technologies. The investigation of the fundamental properties and integration of two new defect-tolerant device concepts is proposed, enabled by novel 2D and 3D topological insulators (TIs), that exhibit unprecedented low-power, room temperature performance and functionalities only achievable using these unique materials. This tolerance to defects will enable nanoelectronics beyond the currently known limits and will specifically impact the national grand challenge of enabling ultra-low-power, post-silicon electronics and represent significant progress in an area of national technological strength, semiconductor electronics. A team of researchers with complementary expertise, including junior investigators complemented by accomplished senior professors, will address the challenges of the proposed work. This research will also broaden scientific and educational participation by creating a pipeline of pre-college and undergraduate students motivated to study science and engineering at universities through, for example, NSF-sponsored Research Experiences for Undergraduates (REU) programs and collaborations with national laboratories and industry partners. The researchers will also engage the public through science cafe programs where faculty members present their research in local pubs and restaurants.This collaborative research team will elucidate the fundamental science and technological implications of new topological insulator (TI)-based nanoelectronic device concepts that can operate at low-power, well above room temperature. Two complementary research threads will be pursued, both of which will enable a new, ultra-low-power, topologically protected device made of bismuth-based materials: 1) a 2D TI-based field-effect transistor that is immune to materials and device imperfections such as defects and line-edge roughness, and 2) a 3D TI-based tunneling device utilizing spin-filtering to exhibit negative differential resistance with unprecedented peak-to-valley ratio performance. TI growth by molecular beam epitaxy (Hinkle) will focus on 2D Bi and 3D Bi2Se3, which have predicted room-temperature device applications. Surface and edge state detection and chemical/structural properties will be investigated using in-situ techniques (Wallace). Theoretical studies including density functional theory (DFT), scattering, and mobility calculations (Vandenberghe) will be employed. Advanced 2- and 3-terminal devices will be fabricated (Banerjee) and these device characteristics will be evaluated in NAND gates. This research will provide materials and device concepts for advanced low-power, high-performance logic, memory, and even oscillatory neuromorphic applications using TIs, a class of devices which are extremely robust against defects/impurities. A TI and 2D materials property and benchmarking database through collaboration with NIST will also be established.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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NNCI: Texas Nanofabrication Facility (TNF)
  • 批准号:
    2025227
  • 项目类别:
    Cooperative Agreement
  • 资助金额:
    $495.0万
  • 财政年份:
    2020
  • 负责人:
    Sanjay Banerjee
  • 依托单位:
NNCI: Texas Nanofabrication Facility (TNF)
  • 批准号:
    1542159
  • 项目类别:
    Cooperative Agreement
  • 资助金额:
    $450.0万
  • 财政年份:
    2015
  • 负责人:
    Sanjay Banerjee
  • 依托单位:
Travel Support Grant to attend the Fourth International Nanotechnology Conference on Communication and Cooperation. To be held on April 14-17, 2008 in Tokyo, Japan.
  • 批准号:
    0826698
  • 项目类别:
    Standard Grant
  • 资助金额:
    $3.0万
  • 财政年份:
    2008
  • 负责人:
    Sanjay Banerjee
  • 依托单位:
Conference: Travel Support Grant to attend the Third International Nanotechnology Conference onCommunication and Cooperation. To be held April 16-19, 2007 in Brussels, Belgium.
  • 批准号:
    0726991
  • 项目类别:
    Standard Grant
  • 资助金额:
    $2.5万
  • 财政年份:
    2007
  • 负责人:
    Sanjay Banerjee
  • 依托单位:
国内基金
海外基金
Research on Quantum Field Theory without a Lagrangian Description
  • 批准号:
    24ZR1403900
  • 项目类别:
    省市级项目
  • 资助金额:
    --
  • 批准年份:
    2024
  • 负责人:
    SATOSHI NAWATA
  • 依托单位:
Cell Research
Cell Research
Cell Research (细胞研究)