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Fault Diagnosis for Yield Improvement and Silicon Debug

Fault Diagnosis for Yield Improvement and Silicon Debug
用于提高良率和芯片调试的故障诊断
批准号:
0306296
负责人:
Tracy Larrabee
金额:
$30.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2003
资助国家:
美国
项目状态:
已结题
起止时间:
2003-08-01 至 2008-07-31

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中文摘要
翻译
制造半导体很困难,让它们正常工作更难,而让它们第一次开机就正常工作几乎是不可能的。造成这种困境的是两种激烈竞争的趋势:现代芯片令人震惊且不断增加的复杂性,以及现代技术产品周期对上市时间的要求越来越长。你可以花一些时间制作一个高度复杂的产品,或者你可以快速制作一个简单的产品,但是快速制作一个高度复杂的产品是非常困难的。不幸的是,这正是当今半导体公司所面临的困境。我们对这些市场趋势无能为力,而且有利可图的产品总是很复杂,很难打造。但是,我们可以做一些事情来解决这个令人望而生畏的任务,即找出数百万晶体管电路拒绝正常工作的问题。这就是我们在故障诊断和硅调试方面的工作。我们正在研究快速而准确地确定缺陷芯片故障的根本原因的方法,即使许多独立的错误导致了单一的不良结果。我们已经开发了算法来分析电路故障的方式,然后使用有关电路本身的信息来推断最可能的故障原因。我们考虑了许多类型的电路故障,从逻辑错误到间歇或定时故障,并针对一系列缺陷机制,从常见的制造错误到复杂和奇异的缺陷场景。我们正在构建与行业标准数据格式和工具流兼容的工具,以便我们的工作能够立即获得行业效益。我们的研究目标是开发复杂而高效的算法,以应对现代芯片可能出现的各种各样的故障。如果半导体行业要实现以更低的成本和更短的上市时间生产更高质量的产品这一(几乎)不可能完成的任务,那么良好的诊断和调试工具是必要的。
英文摘要
Manufacturing semiconductors is hard, making them work right is even harder, and making them work right the first time you turn them on is damn near impossible. This difficult situation is caused by two strongly competing trends: the astounding and ever-increasing complexity of modern chips, and the ever-greater time-to-market demands of the modern technology product cycle. You can take some time and make a highly complex product, or you can make a simple product quickly, but it is extremely hard to make a highly-complex product very quickly. Unfortunately, this is exactly the dilemma faced by today's semiconductor companies.We can't do anything about these market trends, and profitable products will always be complex and hard to build. But, we can do something about the daunting task of figuring out what is wrong with a many-million-transistor circuit that simply refuses to operate properly. This is where our work on fault diagnosis and silicon debug comes in.We are working on ways of quickly but accurately determining the root cause of failure on a defective chip, even when many independent errors contribute to a single bad result. We have developed algorithms that analyze the way a circuit fails, and then use information about the circuit itself to infer the most likely cause of failure. We consider many types of circuit failure, from logic errors to intermittent or timing failures, and are targeting a range of defect mechanisms from common fabrication errors to complex and exotic defect scenarios. We are building tools that will be compatible with industry-standard data formats and toolflows so that our work can have immediate industrial benefit.The goal of our research is to develop sophisticated but efficient algorithms that can deal with the enormous variety of ways that a modern chip can fail. Good diagnosis and debug tools are necessary if the semiconductor industry is to pursue its (nearly) impossible task of producing of higher-quality products at less expense and an ever-shorter time-to-market.
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Mixed-Model Fault Diagnosis
  • 批准号:
    9971172
  • 项目类别:
    Standard Grant
  • 资助金额:
    $21.31万
  • 财政年份:
    1999
  • 负责人:
    Tracy Larrabee
  • 依托单位:
PYI: Sequential and Combinational Test Pattern Generation for Realistic Faults Using Boolean Satisfiability
  • 批准号:
    9158490
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $34.6万
  • 财政年份:
    1991
  • 负责人:
    Tracy Larrabee
  • 依托单位:
RIA: The Application of Boolean Satisfiability Test Pattern Generation for Non-Stuck-At Faults
  • 批准号:
    9011254
  • 项目类别:
    Standard Grant
  • 资助金额:
    $7.74万
  • 财政年份:
    1990
  • 负责人:
    Tracy Larrabee
  • 依托单位:
海外基金