ITR: A Hardware/Compiler Co-Design Approach to Software Protection

ITR：一种硬件/编译器协同设计的软件保护方法

• 批准号: 0325207
• 负责人: Rahul Simha
• 金额: $ 100万
• 依托单位: George Washington University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-01 至 2010-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0325207&HistoricalAwards=false
• 关键词: ITR; Hardware; Compiler; Co; Design

ITR: A Compiler-Hardware Co-Design Approach to Software ProtectionPI's: Rahul Simha, Bhagi Narahari, Alok Choudhary, Nasir MemonAbstract:The growing area of software protection aims to address the problems of code understanding and code tampering along with related problems such as authorization. This project will combine novel techniques in the areas of compilers, architecture, and software security to provide a new, efficient, and tunable approach to some problems in software protection. The goal is to address a broad array of research issues that will ultimately enable design tools such as compilers to assist system designers in managing the tradeoffs between security and performance.The main idea behind the proposed approach is to hide code sequences (keys) within instructions in executables that are then interpreted by supporting FPGA (Field Programmable Gate Array) hardware to provide both a "language" (the code sequences) and a "virtual machine within a machine" (the FPGA) that will allow designers considerable flexibility in providing software protection. Thus, by using long sequences and PKI to exchange a secret key with the FPGA while also encrypting the executable with that secret key, a system can be positioned at the high-security (but low-performance) end of the spectrum. Similarly, as will be explained in the proposal, by using shorter sequences and selective encryption, one can achieve high-performance with higher security than is possible with systems that rely only on obscurity.

ITR：软件保护的硬件协同设计方法PI's：Rahul Simha，Bhagi Narahari，Alok Choudhary，Nasir Memon摘要：软件保护领域的不断增长旨在解决代码理解和代码篡改的问题，沿着相关问题，如授权。本计画将结合联合收割机在编译器、架构、软体安全等领域的新技术，提供一种新的、有效的、可调整的方法来解决软体保护中的一些问题。目标是解决一系列广泛的研究问题，最终使编译器等设计工具能够帮助系统设计人员管理安全性和性能之间的权衡。所提出的方法背后的主要思想是将代码序列（密钥）隐藏在可执行程序中的指令中，然后通过支持FPGA来解释这些指令（现场可编程门阵列）硬件提供“语言”（代码序列）和“机内虚拟机”（FPGA），这将使设计人员在提供软件保护方面具有相当大的灵活性。因此，通过使用长序列和PKI与FPGA交换密钥，同时还使用该密钥加密可执行文件，系统可以定位在频谱的高安全性（但低性能）端。类似地，如将在提案中所解释的，通过使用较短的序列和选择性加密，可以实现比仅依赖于模糊性的系统更高安全性的高性能。