CAREER: Microarchitecture Considerations for Soft-Error Tolerance in Future Microprocessors

职业：未来微处理器中软错误容错的微架构考虑因素

• 批准号: 0347568
• 负责人: James Hoe
• 金额: $ 41万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-01-15 至 2008-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0347568&HistoricalAwards=false
• 关键词: CAREER; Microarchitecture; Considerations; Soft; Error

CAREER: Microarchitecture Considerations for Soft-Error Tolerance in Future MicroprocessorsAbstractThis project addresses the pressing issue of increasing susceptibility to soft errors in future deep-submicron microprocessor implementations. The study develops and evaluates three candidate approaches for detecting and recovering from soft errors. The three approaches are dynamic instruction re-executions in a superscalar processor, redundant executions over two mirrored processor cores facilitated by an efficient crosschecking mechanism, and an all-software approach for unmodified simultaneous multithreading (SMT) processors or chip-multiprocessors (CMP). The study evaluates the potential of each approach and analyzes their trade-off in terms of performance, fault coverage, design complexity and implementation cost. A goal of this research is to overcome the performance and implementation penalties associated with these approaches. An education component of this project applies executable and synthesizable high-level hardware description formalisms to improve the preciseness of in-class discussions and to enable more insightful out-of-class independent exercises.Following decades of exclusive focus on performance, soft-error reliability is one of the key challenges in the continuing advances of microprocessor designs. The results of this research have direct bearing on the multi-billion-dollar microprocessor industry, which in turn will impact our daily experiences from professional to recreational. The results of this research will not only be applicable in the near term to deep-submicron VLSI microprocessors, but may also be extensible to address the reliability of emerging technologies such as quantum, molecular and nano-technologies.

职业：未来微处理器软错误容限的微体系结构考虑摘要本项目解决了未来深亚微米微处理器实现中软错误敏感性增加的紧迫问题。该研究开发和评估三种候选方法检测和恢复软错误。 这三种方法是在超标量处理器中的动态指令重新执行，通过有效的交叉检查机制促进两个镜像处理器核上的冗余执行，以及用于未修改的同时多线程（SMT）处理器或芯片多处理器（CMP）的全软件方法。该研究评估了每种方法的潜力，并分析了它们在性能，故障覆盖率，设计复杂性和实现成本方面的权衡。 本研究的一个目标是克服与这些方法相关的性能和实现惩罚。该项目的教育部分应用可执行和可综合的高级硬件描述形式主义，以提高课堂讨论的精确性，并使更多有见地的课外独立exercises.After几十年的独家专注于性能，软错误的可靠性是在微处理器设计的持续发展的关键挑战之一。 这项研究的结果直接关系到数十亿美元的微处理器行业，这反过来又会影响我们从专业到娱乐的日常体验。 这项研究的结果不仅将在短期内适用于深亚微米超大规模集成电路微处理器，而且还可能扩展到解决新兴技术，如量子，分子和纳米技术的可靠性。