CCF: Small: Accelerating Irregular Algorithms using Cache-Coherent FPGA Accelerators

CCF：小型：使用缓存一致性 FPGA 加速器加速不规则算法

• 批准号: 1618014
• 负责人: James Hoe
• 金额: $ 33万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-08-01 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1618014&HistoricalAwards=false
• 关键词: CCF; Small; Accelerating; Irregular; Algorithms

Until recently, FPGA acceleration of computations has largely focused on algorithms that exhibit a high degree of regularity and predictability in their parallelism and memory access. The advent of high-capacity FPGA accelerators connected to the processor and main memory through a high-performance cache-coherent interconnect enables algorithms with irregular parallelism to be considered. These irregular algorithms, including many data analytic and machine learning kernels, operate on very large, memory-resident, pointer-based data structures. This project will study the opportunity to accelerate irregular algorithms for performance and energy efficiency on emerging cache-coherent FPGA accelerators. The outcome of this investigation has potential for practical commercial impact by helping to establish cache-coherent FPGA acceleration as a viable new platform option for accelerating irregular algorithms that are fundamental to datacenter workloads. This project will also provide valuable training to both graduate and undergraduate students, and improve graduate-level coursework.Instead of the traditional "off-load" model of FPGA acceleration, this project seek to develop a new tightly-coupled FPGA-processor collaboration model that takes advantage of the low-latency, fine-grain shared-memory interactions between the processor and FPGA that are now possible. The project studies fine-grain concurrent mappings of irregular algorithms where the processor and FPGA work together---each leveraging its own characteristic advantages, e.g., large cache, high frequency ALUs for the processor and energy-efficient spatial hardware concurrency for the FPGA---to outperform what either can achieve alone. An integral part of the investigation is also to develop new insights toward what should cache-coherent FPGA accelerators ultimately look like, especially with the support for irregular algorithms in mind.

直到最近，FPGA加速计算主要集中在算法，表现出高度的规律性和可预测性，在他们的并行性和内存访问。通过高性能高速缓存一致性互连连接到处理器和主存储器的高容量FPGA加速器的出现使得可以考虑具有不规则并行性的算法。这些不规则算法，包括许多数据分析和机器学习内核，对非常大的、驻留内存的、基于指针的数据结构进行操作。该项目将研究在新兴的高速缓存一致性FPGA加速器上加速不规则算法以提高性能和能效的机会。这项调查的结果有可能产生实际的商业影响，因为它有助于建立高速缓存一致性FPGA加速，作为一种可行的新平台选项，用于加速数据中心工作负载的基础不规则算法。该项目还将为研究生和本科生提供有价值的培训，并改善研究生水平的课程。该项目旨在开发一种新的紧密耦合的FPGA-处理器协作模型，而不是传统的FPGA加速“卸载”模型，该模型利用了处理器和FPGA之间的低延迟、细粒度共享内存交互。该项目研究了处理器和FPGA协同工作的不规则算法的细粒度并发映射-每个算法都利用了自己的特征优势，例如，大缓存、处理器的高频率ALU和FPGA的节能空间硬件并发性-超越任何一个单独实现的性能。调查的一个组成部分也是对缓存一致性FPGA加速器最终应该是什么样子的发展新的见解，特别是考虑到对不规则算法的支持。