SHF: Small: Compiling Custom Hardware Accelerators from Graph Algorithms

SHF：小型：根据图算法编译定制硬件加速器

• 批准号: 1320725
• 负责人: James Hoe
• 金额: $ 45万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-07-01 至 2017-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320725&HistoricalAwards=false
• 关键词: SHF; Small; Compiling; Custom; Hardware

Many emerging applications in machine learning and data mining can be cast as graph computations. Efficient low-power implementations of graph computations promise disruptive capabilities for the increasingly ubiquitous embedded and mobile platforms. The project is building the GraphGen compiler to overcome the complexity and difficulty of creating graph computation hardware accelerators that are needed to meet the demanding power and performance constraints of embedded and mobile systems. The GraphGen compiler is a general-purpose compiler (within the graph computation domain) to handle arbitrary graph applications based on varying graph structures (e.g., grid-shaped, planar, natural graphs) that may be static or dynamically changing (e.g., updated by streaming data) following different execution strategies (e.g., synchronous vs. asynchronous). GraphGen implementation mapping makes use of reusable hardware implementation templates to allow the same graph computation specification to be efficiently mapped onto different target platforms. Overall, the GraphGen compiler captures knowledge from both application developers (in graph specifications) and hardware designers (in the reusable implementation templates), and bridges the gap between the two camps through automatic mapping of a specification to a template to yield a highly efficient embedded implementation tuned to the application developer's design objectives.The continued exponential increase in transistors-per-die, coupled with advances in sensors and breakthrough algorithms in machine learning and data mining, have resulted in a revolution in the embedded and mobile application space. Graph computation is an important enabling computation paradigm for many of these emerging applications. The GraphGen compiler can facilitate rapid adoption of these applications into embedded and mobile devices by allowing domain experts to automatically translate their graph computation algorithms onto efficient FPGA-accelerated embedded platforms. This new capability has the potential to spark new research in graph computation and embedded hardware architectures by providing a common design automation environment that bridges the gap between application domain experts and hardware designers, thus benefiting industry.

机器学习和数据挖掘中的许多新兴应用都可以转换为图计算。图形计算的高效低功耗实现为日益普遍的嵌入式和移动的平台提供了颠覆性的能力。该项目正在构建GraphGen编译器，以克服创建图形计算硬件加速器的复杂性和困难，这些加速器需要满足嵌入式和移动的系统苛刻的功耗和性能限制。 GraphGen编译器是通用编译器（在图计算域内），用于基于不同的图结构（例如，网格形状的、平面的、自然的图形），其可以是静态的或动态变化的（例如，通过流数据更新）遵循不同的执行策略（例如，同步与异步）。 GraphGen实现映射利用可重用的硬件实现模板，允许将相同的图计算规范有效地映射到不同的目标平台上。 总的来说，GraphGen编译器从两个应用程序开发人员那里获取知识（在图形规范中）和硬件设计人员（在可重用的实现模板中），并通过将规范自动映射到模板来弥合两个阵营之间的差距，以产生针对应用开发人员的设计目标进行调整的高效嵌入式实现。再加上传感器的进步以及机器学习和数据挖掘中的突破性算法，导致了嵌入式和移动的应用空间的革命。图计算是许多新兴应用的重要计算范例。GraphGen编译器允许领域专家将其图形计算算法自动转换到高效的FPGA加速嵌入式平台上，从而有助于将这些应用程序快速应用到嵌入式和移动的设备中。这种新的能力有可能通过提供一个通用的设计自动化环境，弥合应用领域专家和硬件设计师之间的差距，从而使行业受益，从而激发图形计算和嵌入式硬件架构的新研究。