Baseband Signal Processing Algorithm and VLSI Architecture Co-Design Methodologies for Wireless MIMO Transceivers

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This integrative systems proposal focuses on the development of algorithm and VLSI architecture co-design methodologies for implementing baseband signal processing building blocks in high data rate wireless multiple-input multiple-output (MIMO) transceivers. MIMO recently emerged as the almost only viable path to launch very high data rate wireless networks at no cost of extra spectrum and transmission power. However, the complex baseband signal processing makes it a challenge to realize the capacity promised by MIMO in the real world. The intellectual merit of this proposal lies in the research theme of jointly considering algorithm development and VLSI architecture design to tackle the MIMO baseband signal processing implementation challenge. Applying a parallelism/regularity-driven algorithm/architecture co-design methodology, we will develop co-design solutions for three major baseband signal processing blocks in wireless MIMO transceivers, including near-optimum non-linear hard/soft-output MIMO signal detector, limited search state-parallel convolutional code hard/soft-output decoder, and low-density parity-check (LDPC) code encoder/decoder. The Broader Impacts: The education objective of this proposal is to promote the education of VLSI signal processing, the inter-disciplinary area linking semiconductor and signal processing/communication, to a wider spectrum of students. This research has broad impact in the design and effectiveness of high data rate wireless networks that will have great importance to national economy and security and will be ubiquitous in homes, schools, city streets, and airports of the 21st century. It will also benefit many other real-life applications such as optical communications, copper-wired networks, and magnetic/holographic storage, where LDPC coding, convolutional code decoding, and/or MIMO signal detection may be core signal processing functions.