Collaborative Research: CPA-DA: Noise-Aware VLSI Signal Processing: A New Paradigm for Signal Processing Integrated Circuit Design in Nanoscale Era

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PI: Zhang, Tong & Parhi, KeshabProposal No: 0810992 & 0811456Title: Collaborative Research: CPA-DA: Noise-Aware VLSI Signal Processing: A New Paradigm for Signal Processing Integrated Circuit Design in Nanoscale EraInstitution: Rensselaer Polytechnic Institute & University of MinnesotaABSTRACTThe objective of this proposal is to develop a new noise-aware design methodology that can maximize the error resilience of signal processing integrated circuits. As CMOS technology approaches its end-of-roadmap physical limit, there have been increasing levels of environmental and process variations, and susceptibility to noise, which make it a challenge to maintain the historical yield and reliability. This proposal will develop methodology and approaches that tackle this grand challenge in the context of signal processing integrated circuits implementation. The intellectual merit of this proposal lies in the research theme of leveraging the unique characteristics of signal processing functions to substantially improve the tolerance to noise. There are two major parts to this project: developing noise analysis techniques for signal processing integrated circuits, and exploring design space for noise-aware VLSI signal processing. In particular, this research will develop analysis techniques that can quantitatively estimate how variations in signal processing integrated circuits may affect the signal processing performance. This research will further explore the design space for noise-aware VLSI signal processing where the objective is to minimize the noise-induced signal processing performance degradation at minimal energy consumption and/or silicon cost. The proposed research program represents the first step towards exploring a new research area. If successful, it will have broad impact on the semiconductor industry and national economy in both the near term and long term: In the near term, it will generate considerable economic benefit by improving the noise tolerance and the effective yield of signal processing integrated circuits. From another perspective, it will enable more aggressive CMOS scaling for implementing signal processing integrated circuits, which will be greatly beneficial since the signal processing functions are typically very hardware resource demanding. In the long term, this research will shed light on signal processing system implementation using post-silicon nanotechnology, such as molecular electronics, where a significant degree of noise is presumably inevitable. The education objective of this proposal is to promote the education of VLSI signal processing, the inter-disciplinary area linking semiconductor and signal processing/communication, to a wider spectrum of students.