Collaborative Research: CPA-DA: Noise-Aware VLSI Signal Processing: A New Paradigm for Signal Processing Integrated Circuit Design in Nanoscale Era

项目编号：0810992 &amp； Parhi， keshab题目：合作研究：CPA-DA：噪声感知VLSI信号处理：纳米级信号处理集成电路设计的新范例机构：伦斯勒理工学院和明尼苏达大学摘要本提案的目标是开发一种新的噪声感知设计方法，可以最大限度地提高信号处理集成电路的容错能力。随着CMOS技术接近其路线图的物理极限，环境和工艺变化的水平越来越高，对噪声的敏感性也越来越高，这使得保持历史产量和可靠性成为一项挑战。本提案将开发方法和方法，以解决信号处理集成电路实现背景下的这一重大挑战。该方案的智力优势在于其研究主题是利用信号处理函数的独特特性来大幅提高对噪声的容忍度。这个项目有两个主要部分：开发信号处理集成电路的噪声分析技术，以及探索噪声感知VLSI信号处理的设计空间。特别是，本研究将开发分析技术，可以定量地估计信号处理集成电路的变化如何影响信号处理性能。本研究将进一步探索噪声感知VLSI信号处理的设计空间，其目标是在最小的能耗和/或硅成本下最大限度地减少噪声引起的信号处理性能下降。提出的研究计划是探索新研究领域的第一步。如果成功，将在近期和长期对半导体产业和国民经济产生广泛的影响：近期内，通过提高信号处理集成电路的噪声容限和有效良率，将产生可观的经济效益。从另一个角度来看，它将使更积极的CMOS缩放实现信号处理集成电路，这将是非常有益的，因为信号处理功能通常非常需要硬件资源。从长远来看，这项研究将阐明使用后硅纳米技术的信号处理系统实现，例如分子电子学，其中很大程度的噪声可能是不可避免的。该提案的教育目标是促进VLSI信号处理的教育，这是连接半导体和信号处理/通信的跨学科领域，以更广泛的学生。

PI: Zhang, Tong & Parhi, KeshabProposal No: 0810992 & 0811456Title: Collaborative Research: CPA-DA: Noise-Aware VLSI Signal Processing: A New Paradigm for Signal Processing Integrated Circuit Design in Nanoscale EraInstitution: Rensselaer Polytechnic Institute & University of MinnesotaABSTRACTThe objective of this proposal is to develop a new noise-aware design methodology that can maximize the error resilience of signal processing integrated circuits. As CMOS technology approaches its end-of-roadmap physical limit, there have been increasing levels of environmental and process variations, and susceptibility to noise, which make it a challenge to maintain the historical yield and reliability. This proposal will develop methodology and approaches that tackle this grand challenge in the context of signal processing integrated circuits implementation. The intellectual merit of this proposal lies in the research theme of leveraging the unique characteristics of signal processing functions to substantially improve the tolerance to noise. There are two major parts to this project: developing noise analysis techniques for signal processing integrated circuits, and exploring design space for noise-aware VLSI signal processing. In particular, this research will develop analysis techniques that can quantitatively estimate how variations in signal processing integrated circuits may affect the signal processing performance. This research will further explore the design space for noise-aware VLSI signal processing where the objective is to minimize the noise-induced signal processing performance degradation at minimal energy consumption and/or silicon cost. The proposed research program represents the first step towards exploring a new research area. If successful, it will have broad impact on the semiconductor industry and national economy in both the near term and long term: In the near term, it will generate considerable economic benefit by improving the noise tolerance and the effective yield of signal processing integrated circuits. From another perspective, it will enable more aggressive CMOS scaling for implementing signal processing integrated circuits, which will be greatly beneficial since the signal processing functions are typically very hardware resource demanding. In the long term, this research will shed light on signal processing system implementation using post-silicon nanotechnology, such as molecular electronics, where a significant degree of noise is presumably inevitable. The education objective of this proposal is to promote the education of VLSI signal processing, the inter-disciplinary area linking semiconductor and signal processing/communication, to a wider spectrum of students.