Design of Energy-Efficient Programmable Signal Processing Accelerators in 3D Integrated Heterogeneous Multi-Core Processor for Mobile Multimedia Communication

本研究的目的是利用三维（3D）集成技术为异构多核移动多媒体通信处理器开发节能的可编程信号处理加速器。该方法是利用三维逻辑存储器集成所带来的海量存储容量和极高的逻辑存储器数据带宽，通过将高性能逻辑芯片和高密度存储芯片垂直堆叠在一起来实现，充分利用大多数信号处理功能固有的并行性。智力上的优点在于研究主题将信号处理算法、可编程加速器架构和存储器建模与优化结合起来，最有效地利用三维逻辑-存储器集成所提供的独特特性，即存储容量和带宽。在本文提出的研究范围内，研究了视频编码和前向纠错编码系统，这两个系统在移动多媒体通信信号处理中占主导地位。由于动态随机存取存储器（DRAM）的高存储密度，本研究将专注于3D逻辑与DRAM的集成，并以真正的技术感知方式开发准确的3D DRAM建模和性能预测能力。该研究的更广泛影响包括通过提供节能可编程信号处理加速器设计解决方案，大大提高未来移动多媒体通信设备的能源效率。此外，该研究代表了建立三维超大规模集成电路（VLSI）信号处理新领域的第一步，自然地扩展了传统VLSI信号处理领域。该项目还促进了对广大学生在未来纳米级集成电路和3D集成方面的进步的教育。

The objective of this research is to develop energy-efficient programmable signal processing accelerators for heterogeneous multi-core mobile multimedia communication processors utilizing three-dimensional (3D) integration technology. The approach is to use the massive storage capacity and extremely high logic-memory data bandwidth enabled by 3D logic-memory integration, realized by vertically stacking high-performance logic die and high-density memory dies together, to fully exploit the parallelism inherent in most signal processing functions.The intellectual merit lies in the research theme of jointly considering signal processing algorithm, programmable accelerator architecture, and memory modeling and optimization to most effectively exploit the unique features, i.e., storage capacity and bandwidth, provided by 3D logic-memory integration. Within the proposed scope, this research addresses video coding and forward error correction coding systems, which dominate the energy consumption of mobile multimedia communication signal processing. Because of the high storage density of dynamic random access memory (DRAM), this research will focus on 3D logic-DRAM integration and develop accurate 3D DRAM modeling and performance prediction capability in a truly technology-aware manner.The broader impacts of the research include the potential to greatly improve the energy efficiency of future mobile multimedia communication devices by providing energy-efficient programmable signal processing accelerator design solutions. In addition, the research represents a first step towards establishing a new area of 3D very large-scale integration (VLSI) signal processing that naturally expands the traditional VLSI signal processing area. The project also promotes the education of a wide spectrum of students in advances in future nanoscale integrated circuits and 3D integration.