SGER: Innovative Off-Chip Interconnects for 45-nm and sub-45-nm Node ICs

本提案的目标是为45纳米和sub-45纳米节点集成电路设计、制造、组装和测试创新的、高风险和高回报的芯片与衬底互连结构。为了实现该提案的目标，将使用由顺序电镀和光刻组成的类似liga的工艺制造兼容的互连。PI将设计互连，以优化定向机械遵从性、电阻、电感、电容、芯片和衬底之间的不连续、焦耳加热引起的最小温度升高以及抗疲劳失效的可靠性。PI将有适当的原型测试车辆来测试他建议的许多参数。该提案支持IC设计和制造在尺寸，性能，成本和可靠性方面的主要挑战之一。该提案代表了芯片到衬底互连技术的基本范式转变，并提出了一种创新的方法来满足2013年及以后的半导体封装。更广泛的影响：该提案将有利于未来半导体行业的创新技术发展，并可能产生重大的经济影响。这将有助于培养这项技术的研究生。如果这项技术取得成功，那么它不仅将有助于大规模设备应用，而且还将有助于系统封装的开发，这需要仔细和经济有效的互连。

The objective of this proposal is to design, fabricate, assemble, and test innovative, high risk and high payoff compliant chip to substrate interconnect structures for the 45 nm and sub-45nm node ICs. To accomplish the goals of this proposal the will fabricate the compliant interconnects using LIGA-like process consisting of sequential plating and photolithography. The PI will design the interconnects to optimize the directional mechanical compliance, electrical resistance, inductance, capacitance, discontinuity between the chip and substrate, minimum temperature increase due to joule heating, and reliability against fatigue failure. The PI will have appropriate prototype test vehicles to test many of his suggested parametersThis proposal supports one of the major challenges in the IC design and fabrication in terms of size, performance, cost, and reliability. This proposal represents fundamental paradigm shift in chip-to-substrate interconnect technology and presents an innovative approach to meet the semiconductor packaging for 2013 and beyond. The broader impact: This proposal will benefit the semiconductor industry of the future in the development of novel innovative technology and could have significant economic impact. It will help train the graduate students in this technology. If this technology is successful, then it will not only help large-scale device applications but in the development of system in a package, which requires careful and cost effective interconnects.