SGER: Innovative Off-Chip Interconnects for 45-nm and sub-45-nm Node ICs

SGER：适用于 45 纳米和 45 纳米以下节点 IC 的创新片外互连

• 批准号: 0539023
• 负责人: Suresh Sitaraman
• 金额: --
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2005
• 资助国家: 美国
• 起止时间: 2005-08-01 至 2007-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0539023&HistoricalAwards=false
• 关键词: SGER; Innovative; Off; Chip; Interconnects

The objective of this proposal is to design, fabricate, assemble, and test innovative, high risk and high payoff compliant chip to substrate interconnect structures for the 45 nm and sub-45nm node ICs. To accomplish the goals of this proposal the will fabricate the compliant interconnects using LIGA-like process consisting of sequential plating and photolithography. The PI will design the interconnects to optimize the directional mechanical compliance, electrical resistance, inductance, capacitance, discontinuity between the chip and substrate, minimum temperature increase due to joule heating, and reliability against fatigue failure. The PI will have appropriate prototype test vehicles to test many of his suggested parametersThis proposal supports one of the major challenges in the IC design and fabrication in terms of size, performance, cost, and reliability. This proposal represents fundamental paradigm shift in chip-to-substrate interconnect technology and presents an innovative approach to meet the semiconductor packaging for 2013 and beyond. The broader impact: This proposal will benefit the semiconductor industry of the future in the development of novel innovative technology and could have significant economic impact. It will help train the graduate students in this technology. If this technology is successful, then it will not only help large-scale device applications but in the development of system in a package, which requires careful and cost effective interconnects.

本提案的目的是设计、制造、组装和测试创新的、高风险和高回报的45 nm和亚45 nm节点IC的兼容芯片到衬底互连结构。 为了实现这个建议的目标，将使用LIGA类工艺包括顺序电镀和光刻制造的顺应性互连。 PI将设计互连，以优化定向机械顺应性、电阻、电感、电容、芯片和基板之间的不连续性、焦耳热引起的最小温度升高以及抗疲劳失效的可靠性。 PI将有适当的原型测试车辆来测试他建议的许多参数。该提案支持IC设计和制造中的主要挑战之一，包括尺寸、性能、成本和可靠性。 该提案代表了芯片到基板互连技术的根本范式转变，并提出了一种创新方法，以满足2013年及以后的半导体封装。 更广泛的影响：这项建议将有利于未来半导体行业开发新的创新技术，并可能产生重大的经济影响。 这将有助于培养研究生在这项技术。 如果这项技术获得成功，那么它将不仅有助于大规模器件应用，而且有助于系统级封装的开发，这需要仔细且具有成本效益的互连。