DEVELOPMENT OF COMPLIANT FREE-STANDING STRUCTURES FOR SUB 32-nm MULTI-CORE ICs

为低于 32 nm 的多核 IC 开发合规的独立式结构

• 批准号: 0901679
• 负责人: Suresh Sitaraman
• 金额: $ 35万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-15 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0901679&HistoricalAwards=false
• 关键词: DEVELOPMENT; COMPLIANT; FREE; STANDING; STRUCTURES

The objective of this research is to design, fabricate, assemble, characterize, and test innovative compliant, free-standing, parallel-path, off-chip interconnects for next-generation microelectronic systems. The proposed interconnects will be wafer-level, scalable, cost-effective, environmentally-friendly, and reworkable. The approach is to employ a heterogeneous architecture that combines both column and parallel-path compliant interconnects that will be fabricated through sequential lithography and plating processes. By developing electrical and thermo-mechanical simulation models, the interconnect design will be optimized. The proposed compliant interconnects represent a paradigm shift in chip-to-substrate interconnect technology and present an innovative approach to meet the semiconductor packaging requirements for the year 2016 and beyond. Combining the fundamental principles related to material, mechanical, electrical, and thermal characteristics with practical aspects of fabrication, assembly, and testing of interconnects, this high-risk far-reaching approach proposed in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research. Through miniaturization, this program will have a unique impact in areas such as high-speed computing, medical electronics and sensors implanted in the body for health monitoring and drug delivery, integrated digital-RF-opto systems, wireless and portable electronics, and smart "fly" electronics and sensors used for intelligence gathering and bio/chemical sensing. Thus, by impacting computer, communications, consumer, and medical microsystems, this research will provide extensive benefits to the society at large. The research findings will be integrated into classroom instruction and published in journals and conferences. Through student internships and one-to-one mentoring, a diverse mix of students will be motivated to pursue engineering education.

这项研究的目标是为下一代微电子系统设计、制造、组装、表征和测试创新的兼容、独立、并行路径的片外互连。拟议的互连将是晶圆级的、可扩展的、具有成本效益的、环保的和可返工的。该方法是采用一种结合了列和并行路径兼容互连的异质架构，该互连将通过顺序光刻和电镀工艺来制造。通过开发电气和热机械仿真模型，互连设计将得到优化。建议的合规互连代表了芯片到基板互连技术的范式转变，并提出了一种创新的方法，以满足2016年及以后的半导体封装要求。将与材料、机械、电气和热特性相关的基本原理与互连的制造、组装和测试的实际方面相结合，该计划中提出的这种高风险的影响深远的方法超出了电子行业当前的重点，因此适合于基于大学的研究。通过微型化，该计划将在高速计算、医疗电子和植入人体内用于健康监测和药物输送的传感器、集成数字-射频-光学系统、无线和便携式电子以及用于情报收集和生物/化学传感的智能“飞行”电子和传感器等领域产生独特的影响。因此，通过影响计算机、通信、消费者和医疗微系统，这项研究将为整个社会提供广泛的好处。研究成果将被整合到课堂教学中，并在期刊和会议上发表。通过学生实习和一对一指导，各种各样的学生将被激励去追求工程教育。