Exploring Design Approaches and Fault Tolerance in Nano Streaming Processors

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Nanotechnology has emerged in recent years as a promising technological platform for new computational structures. Substantial research has been carried out into hardware based on nanotubes and nanowires: structures which have feature sizes of just a few nanometers. The principal objective of the project is to develop the foundations for nanoscale computational structures, circuits and architectures, that will take advantage of the unique properties of nanoscale devices. In particular, the defect density of nanodevices is expected to be much greater than that of conventional microelectronic devices. Fault-tolerance techniques to allow circuits containing faults to still continue to function will be developed. Fault tolerance always requires introducing redundancy; fault-tolerant design involves making tradeoffs between the overhead imposed by such redundancy and the available gain in reliability. Design tools for synthesizing computer architectures based on nanotechnology will be developed. Such tools will take into consideration realistic parameters and physical constraints that affect the placement of nanocircuits, and will allow the designer to study architectural tradeoffs in nanotechnology.