Exploring Design Approaches and Fault Tolerance in Nano Streaming Processors

探索纳米流处理器的设计方法和容错能力

• 批准号: 0541066
• 负责人: Csaba Andras Moritz
• 金额: --
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-01 至 2010-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541066&HistoricalAwards=false
• 关键词: Exploring; Design; Approaches; Fault; Tolerance

Nanotechnology has emerged in recent years as a promising technological platform for new computational structures. Substantial research has been carried out into hardware based on nanotubes and nanowires: structures which have feature sizes of just a few nanometers. The principal objective of the project is to develop the foundations for nanoscale computational structures, circuits and architectures, that will take advantage of the unique properties of nanoscale devices. In particular, the defect density of nanodevices is expected to be much greater than that of conventional microelectronic devices. Fault-tolerance techniques to allow circuits containing faults to still continue to function will be developed. Fault tolerance always requires introducing redundancy; fault-tolerant design involves making tradeoffs between the overhead imposed by such redundancy and the available gain in reliability. Design tools for synthesizing computer architectures based on nanotechnology will be developed. Such tools will take into consideration realistic parameters and physical constraints that affect the placement of nanocircuits, and will allow the designer to study architectural tradeoffs in nanotechnology.

近年来，纳米技术作为一种有前途的技术平台出现在新的计算结构中。基于纳米管和纳米线的硬件已经进行了大量的研究，这些结构的特征尺寸只有几纳米。该项目的主要目标是开发纳米级计算结构、电路和架构的基础，这将利用纳米级器件的独特特性。特别是，纳米器件的缺陷密度有望比传统的微电子器件大得多。允许包含故障的电路仍然继续工作的容错技术将被开发出来。容错总是需要引入冗余；容错设计涉及在这种冗余带来的开销和可靠性方面的可用增益之间进行权衡。开发基于纳米技术的综合计算机体系结构的设计工具。这些工具将考虑到影响纳米电路放置的现实参数和物理限制，并且将允许设计者研究纳米技术的架构权衡。