SHF: Medium: Architecting 3D Integrated Circuit Fabrics at Nanoscale

在这个项目中，一种新的纳米级三维(3-D)集成电路技术正在研究中，该技术可能会给微电子行业带来革命性的影响，并产生深远的社会经济影响。目前的二维(2-D)互补金属氧化物半导体(CMOS)技术是构建用于计算机、移动设备、医疗和空间应用、工业应用和其他嵌入式设备的集成电路的主要主力。虽然这种在上个世纪发明并一直是全球社会经济进步的关键驱动力的cmos技术，预计很快就会达到基本的物理极限，无法提供我们习惯的改善。该项目为集成电路的持续小型化提供了新的方向，实现了持续的可伸缩性，具有数量级的效率优势，包括降低成本，以及减少维持高性能应用所需的耗电量。这些改进正在改变游戏规则，预计将推动许多新应用领域的创新。另一个关键方面是教育和推广部分，使学生和更广泛的技术界受益。这包括创业指导、支持本科生接受先进的跨学科纳米技术概念培训、国际合作以及通过在线技术广泛传播研究成果。虽然不断扩展的CMOS集成电路架构一直是集成电路行业的主要驱动力，但由于基本的物理限制，扩展到20 nm以下的技术被证明是非常困难的。随着效益的放缓，迁移到真正的3-D将难以实现：其定制和制造的核心要求与精细的3-D集成本质上并不兼容。该项目提出了一种全面的3-D集成电路布料技术，其中核心布料方面统一开发，以实现3-D兼容性。具有垂直纳米线的织物纳米结构和用于连接和3-D热管理的架构化解决方案，以及跨设备、电路和可制造性的跨层方法，是这一方法的关键。对这种3-D纳米芯片(包括设计的4位微处理器)的初步评估表明，密度提高了60倍以上，性能/瓦特提高了16.5倍以上，对于超大规模设计来说，有可能达到两个数量级。分析预测承诺在按比例调整的cmos的基础上进一步改进。研究将集中在纳米级核心结构的详细设计方面，包括材料选择和设计规则，使用自下而上的方法进行综合评估，包括材料考虑，以及纳米电路/体系结构级别的设计和模拟。实验研究将集中在核心结构方面的验证。电子束光刻将与标准半导体制造工艺一起用于实验洁净室演示。

In this project, a new nanoscale three-dimensional (3-D) integrated circuit technology that can potentially revolutionize the microelectronics industry with far-reaching socio-economic impact is being investigated. The current two-dimensional (2-D) Complementary Metal Oxide Semiconductor (CMOS) technology is the main workhorse for building integrated circuits for computers, mobile devices, medical and space applications, industrial applications, and other embedded devices. While this CMOS technology, that was invented in the last century and ever since remained a key driver of global socio-economic progress, is soon expected to reach fundamental physical limits and will not be able to provide the improvements we are accustomed to. This project provides a new direction for continuous miniaturization of integrated circuits enabling continuous scaling with orders of magnitude efficiency benefits including reduced cost, as well as, a reduction of the amount of power consumption required to sustain applications at high performance. These improvements are game changing and are expected to fuel innovation in many new application domains. Another key aspect is the educational and outreach component, benefiting students and the broader technical community. This includes entrepreneurship mentoring, supporting undergraduate students for training in advanced cross-disciplinary nanotechnology concepts, international collaborations, and broad research dissemination through online technologies. While continuous scaling of the CMOS integrated circuit architecture has been the major driver for the integrated circuits industry, scaling to sub-20nm technologies is proving to be very difficult due to fundamental physical limits. As the benefits are slowing, migrating to true 3-D eludes CMOS: its core requirements of customization and manufacturing are not inherently compatible with fine-grain 3-D integration. This project proposes a comprehensive 3-D integrated circuit fabric technology in which core fabric aspects are developed in unison to achieve 3-D compatibility. Fabric nanostructures with vertical nanowires and architected solutions for connectivity and 3-D heat management, in conjunction with a cross-layer approach across device, circuit and manufacturability, are essential to this approach. Preliminary evaluations for this 3-D nanofabric, including a designed 4-bit microprocessor, show more than 60x improvement in density with greater than 16.5x improvement in performance/watt and a potential for two orders of magnitude for very large-scale designs. Analytical projections promise further improvements over scaled CMOS. The research will focus on detailed design of core fabric aspects at nanoscale including material choices and design rules, comprehensive evaluation using a bottom-up methodology including material considerations, and nanocircuit/architecture-level designs and simulations. Experimental research will focus on validation of core fabric aspects. E-beam lithography will be used along with standard semiconductor manufacturing processes for experimental cleanroom demonstrations.