Efficient Fine Grained Synchronization Support Using Full/Empty Tagged Shared Memory and Cache Coherency

同步通过强制执行真正的数据依赖关系和时间约束来确保并行执行的正确性。在基于共享内存编程模型的并行编程环境中，同步既可以通过显式的用户级粗粒度同步原语(如锁和障碍)提供，也可以通过隐式同步的数据结构提供，如可锁的L结构和一次性写入I结构。我们建议设计一种全/空标记存储器层次结构，该层次结构具有对细粒度同步的积极硬件支持，并且嵌入在SMP或NUMA多处理器或单芯片多处理器的高速缓存一致性机制中。我们建议以类似于在无锁定高速缓存中高速缓存未命中的方式来处理同步故障。我们认为，同时处理同步和一致性可以提供更有效的执行，减少内存控制器的占用和协议消息消耗的网络带宽。性能优势主要是在编程模型中允许数据流风格的计算的结果，并通过最小化粗粒度同步导致的错误依赖的可能性来最大化公开的并行性。

Synchronization insures correctness of parallel execution by enforcing true data dependencies and timing constraints. In a parallel programming environment based on the shared-memory programming model, synchronization is provided either through explicit user-level coarse-grain synchronization primitives (such as locks and barriers) or implicitly synchronized data structures such as lock-able L-structures and write-once I-structures.In this project we propose a new efficient way to support fine grained synchronization mechanismson multiprocessors. We propose to design a full/empty tagged memory hierarchy with aggressive hardware support for fine grained synchronization that is embedded in the cache coherency mechanism of an SMP or a NUMA multiprocessor, or a single-chip multiprocessor. We propose to handle synchronization faults in a similar way as cache misses in a lockup-free cache. We believe that handling synchronization and coherence together can provide a more efficient execution, reducing the occupancy in the memory controllers and the network bandwidth consumed by protocol messages. The performance benefits are primarily the result of allowing a dataflow style of computation in programming models, and maximizing the exposed parallelism by minimizing the possibility of false dependencies caused by coarse grained synchronization.