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Efficient Fine Grained Synchronization Support Using Full/Empty Tagged Shared Memory and Cache Coherency

使用完整/空标记共享内存和缓存一致性的高效细粒度同步支持

基本信息

批准号：
0105516
负责人：
Csaba Andras Moritz
金额：
$ 22.5万
依托单位：
University of Massachusetts Amherst
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2001
资助国家：
美国
起止时间：
2001-08-01 至 2005-07-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=0105516&HistoricalAwards=false
关键词：
Efficient Fine Grained Synchronization Support

项目摘要

Synchronization insures correctness of parallel execution by enforcing true data dependencies and timing constraints. In a parallel programming environment based on the shared-memory programming model, synchronization is provided either through explicit user-level coarse-grain synchronization primitives (such as locks and barriers) or implicitly synchronized data structures such as lock-able L-structures and write-once I-structures.In this project we propose a new efficient way to support fine grained synchronization mechanismson multiprocessors. We propose to design a full/empty tagged memory hierarchy with aggressive hardware support for fine grained synchronization that is embedded in the cache coherency mechanism of an SMP or a NUMA multiprocessor, or a single-chip multiprocessor. We propose to handle synchronization faults in a similar way as cache misses in a lockup-free cache. We believe that handling synchronization and coherence together can provide a more efficient execution, reducing the occupancy in the memory controllers and the network bandwidth consumed by protocol messages. The performance benefits are primarily the result of allowing a dataflow style of computation in programming models, and maximizing the exposed parallelism by minimizing the possibility of false dependencies caused by coarse grained synchronization.

同步通过强制执行真实的数据依赖性和时间约束来确保并行执行的正确性。在基于共享内存编程模型的并行程序设计环境中，同步可以通过显式的用户级粗粒度同步原语（如锁和屏障）或隐式的同步数据结构（如可锁L结构和一次写入I结构）来提供，本文提出了一种新的有效方法来支持多处理器上的细粒度同步机制。我们建议设计一个完整的/空的标记的存储器层次结构与积极的硬件支持细粒度的同步，是嵌入在该高速缓存一致性机制的SMP或NUMA多处理器，或单芯片多处理器。我们建议以与无锁定缓存中的缓存未命中类似的方式处理同步错误。我们相信，处理同步和一致性在一起可以提供一个更有效的执行，减少占用内存控制器和协议消息消耗的网络带宽。性能优势主要是由于允许在编程模型中进行低粒度的计算，并通过最小化粗粒度同步导致的错误依赖的可能性来最大化暴露的并行性。