Statistical Tools and Methodologies for Timing Validation and Silicon Debug

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ABSTRACT0541192Wang, Li-ChungU of Cal Santa BarbaraProject Title: Statistical Tools and Methodologies for Timing Validation and Silicon DebugWith the advances to nanometer manufacturing technologies, the gap between chip design and chip manufacturing has become wider due to increased parametric variations. This gap causes the reduction in percentage of good parts coming out of an advanced manufacturing line, resulting in significant loss of manufacturing resources. Bridging the gap demands novel tools and methodologies in design validation and silicon debug. This project proposes a novel validation and debug framework that facilitates the automatic information flow between manufacturing testing and design simulation. Integrated with the planned educational activities, the research proposes a coherent software framework consists of three components: (1) pattern-based statistical timing analysis, (2) silicon emulation, (3) test data mining. The primary goal of pattern-based statistical timing analysis is to enable robust test development and silicon chip debug. It is a simulation tool that analyzes the sensitivity of test results with respect to model assumptions and process variations. To better understand the gap between design and manufacturing, a careful study on how different parametric variations interact to impact chip performance is required. To enable this study, the PI proposes the development of a silicon emulator that exposes the complexity of performance variations in a simulation environment. In the third component, novel data mining and statistical learning techniques will be developed to extract useful design information from test data. Novel debug and validation methodologies that incorporate the test simulation tool and test data mining techniques will be developed to facilitate the convergence between design and manufacturing. This research complements other research efforts in the design automation and test areas. While the research in statistical static timing analysis aims to provide new tools to better cope with variations in reaching timing closure, the proposed framework aims to resolve the issues after the timing closure. While the research in delay testing aims to enhance the effectiveness of screening frequency-dependent manufacturing defects, the proposed framework aims to effectively diagnose the discrepancies between design behavior and silicon chip behavior. This research introduces novel applications of data mining and statistical learning techniques. While most data mining techniques focus on model predictability and accuracy, the proposed techniques will focus on model interpretability and diagnosis. These new techniques can inspire the data mining community to develop novel approaches to be applied in design automation and manufacturing test applications. Technologies developed through the project will be transferred to the leading semiconductor companies. These technologies will improve their design and test methodologies and continue the push of manufacturing technologies to the cutting edge.