Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

先进技术中模拟和射频集成电路的协同综合方法和计算机辅助设计工具

• 批准号: 342185-2013
• 负责人: Zhang, Lihong
• 金额: $ 2.11万
• 依托单位: Memorial University of Newfoundland
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=669690
• 关键词: Synergistic; Synthesis; Methodologies; Computer; Aided

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. **In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. **Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.****************

在90nm及以下的技术中，晶体管性能受到外在布局依赖效应（LDEs）的强烈影响，例如晶体管井邻近和应力效应。最近的研究表明，在纳米工艺节点上忽略lde会导致晶体管性能变化15%-30%，这很容易导致模拟/射频集成电路（IC）的故障。当使用领先的商用模拟/射频设计方法时，相关的LDE对电路性能的影响在布局生成之前是未知的。因此，在先进的技术中，不可避免地需要大量的设计迭代和人工干预。**本研究项目将研究协同综合方法和计算机辅助设计工具，实现性能优化与物理效果的融合。提出了一种LDE感知和变化感知电路拓扑综合方法，该方法可以通过考虑相关布局影响来有效地主动探索搜索空间。本文将研究一种新的两阶段LDE、变化和寄生感知电路尺寸方法，该方法首先采用基于符号方程的快速全局优化方案，然后采用基于仿真的精确尺寸方法。我们还将研究自动布局综合策略，以解决LDE，变异和寄生相关的约束。**由于对复杂模拟效果的高灵敏度，模拟/射频ic已被公认为快速将混合信号系统片上产品推向市场的设计瓶颈。在全球范围内，模拟/射频集成电路的lde感知合成中的系统对策尚未得到解决。由于具有巨大的商业化潜力，该研究计划解决了越来越具有挑战性的LDE问题及其深刻的互动性，这对于纳米技术中的模拟/射频IC合成是不可忽视的。该计划将通过显著提高设计效率和可靠性，使模拟/射频设计界受益，并将增强加拿大在该领域的竞争优势。****************