Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

90 nm及以下工艺的晶体管性能受到外部布局相关效应（LDE）的强烈影响，例如晶体管阱邻近效应和应力效应。最近的研究表明，在纳米工艺节点处忽略LDE会导致晶体管性能的15%-30%的变化，这可能容易导致模拟/RF集成电路（IC）的故障。当使用领先的商用模拟/RF设计方法时，在生成布局之前，相关的LDE对电路性能的影响是未知的。因此，在先进技术中不可避免地需要大量的设计迭代以及人工干预。** 在本研究计划中，将研究协同合成方法和计算机辅助设计工具，以实现性能优化和物理效果之间的融合。一个LDE和变化感知的电路拓扑综合方法，它可以有效地探索搜索空间主动考虑相关的布局的影响，将开发。一种新的两阶段的LDE，变化和寄生感知的电路规模的方法，首先部署了一个符号方程为基础的计划，快速全局优化，然后基于仿真的方法，精细的规模，将被研究。我们还将研究自动布局综合策略，以解决LDE，变异和寄生相关的约束。** 由于对复杂模拟效应的高度敏感性，模拟/RF IC已被认为是迅速将混合信号片上系统产品推向市场的设计瓶颈。模拟/RF IC的LDE感知合成中的系统性对策尚未在全球范围内得到解决。具有巨大的商业化潜力，这项拟议的研究计划解决了日益具有挑战性的LDE问题及其深刻的相互作用的性质，不能忽视的模拟/RF IC合成纳米技术。该计划将通过显著提高设计生产力和可靠性，使模拟/RF设计界受益，并将增强加拿大在该领域的竞争优势。

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. **In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. **Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.****************