ITR: Post-Silicon Validation and Diagnosis Based Upon Statistical Delay Models

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As the manufacturing technologies move toward nanometer ranges, one of the major challenges is to ensure consistency between the behavior expected of a design and its actual behavior in a real silicon chip. Due to Deep Sub-Micron (DSM) effects such as process variations, small defects, and electrical noise, it has become increasingly difficult to predict the design's timing behavior on silicon, or to guarantee such timing behavior before the design goes into production. To avoid slowdowns in manufacturing, the industry needs novel post-silicon validation and diagnosis tools that will effectively resolve the inconsistency between a design model and its implementation on a silicon chip. To meet the challenge, the PIs propose novel statistical approaches that will better model, and more accurately simulate, the timing behavior of a device. The PIs propose three research components in this project to be integrated with their planned educational activities: (1) diagnosis of timing problems, (2) post-silicon validation and debugging, and (3) prediction of timing quality. In diagnosis, techniques will be developed to locate timing problems on faulty chips, determining whether these problems may be due to manufacturing defects. In validation and debugging, techniques will be developed to ensure consistency between the timing behavior of models used to design a chip and that which is observed during the manufacturing process. For the third component, prediction of timing quality, techniques will be developed to draw statistical inference about the timing quality level in the stages of mass production. The proposed research will complement other research efforts in the modeling of DSM circuits and process variations by taking the analysis to a more abstract level. Rather than dealing directly with transistors and wires, the proposed tools will operate on correlated random variables that model the timing behavior of transistors and wires. This project will facilitate the development of practical tools for large and complex designs. When the proposed statistical tools and methodologies become available, chip designers can relax the metrics of various parameters in order to obtain the best design tradeoff, thus pushing manufacturing technologies to the cutting edge. When silicon's timing problems can be more effectively detected and better understood, companies can avoid wasting resources in struggling with manufacturing uncertainties and devote these resources to more productive uses.