ITR: Post-Silicon Validation and Diagnosis Based Upon Statistical Delay Models

ITR：基于统计延迟模型的硅后验证和诊断

• 批准号: 0312701
• 负责人: Li-Chung Wang
• 金额: $ 30万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-01 至 2006-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0312701&HistoricalAwards=false
• 关键词: ITR; Post; Silicon; Validation; Diagnosis

As the manufacturing technologies move toward nanometer ranges, one of the major challenges is to ensure consistency between the behavior expected of a design and its actual behavior in a real silicon chip. Due to Deep Sub-Micron (DSM) effects such as process variations, small defects, and electrical noise, it has become increasingly difficult to predict the design's timing behavior on silicon, or to guarantee such timing behavior before the design goes into production. To avoid slowdowns in manufacturing, the industry needs novel post-silicon validation and diagnosis tools that will effectively resolve the inconsistency between a design model and its implementation on a silicon chip. To meet the challenge, the PIs propose novel statistical approaches that will better model, and more accurately simulate, the timing behavior of a device. The PIs propose three research components in this project to be integrated with their planned educational activities: (1) diagnosis of timing problems, (2) post-silicon validation and debugging, and (3) prediction of timing quality. In diagnosis, techniques will be developed to locate timing problems on faulty chips, determining whether these problems may be due to manufacturing defects. In validation and debugging, techniques will be developed to ensure consistency between the timing behavior of models used to design a chip and that which is observed during the manufacturing process. For the third component, prediction of timing quality, techniques will be developed to draw statistical inference about the timing quality level in the stages of mass production. The proposed research will complement other research efforts in the modeling of DSM circuits and process variations by taking the analysis to a more abstract level. Rather than dealing directly with transistors and wires, the proposed tools will operate on correlated random variables that model the timing behavior of transistors and wires. This project will facilitate the development of practical tools for large and complex designs. When the proposed statistical tools and methodologies become available, chip designers can relax the metrics of various parameters in order to obtain the best design tradeoff, thus pushing manufacturing technologies to the cutting edge. When silicon's timing problems can be more effectively detected and better understood, companies can avoid wasting resources in struggling with manufacturing uncertainties and devote these resources to more productive uses.

随着制造技术向纳米范围发展，主要挑战之一是确保设计的预期行为与其在真实的硅芯片中的实际行为之间的一致性。由于深亚微米（DSM）效应，例如工艺变化、小缺陷和电噪声，预测硅上的设计的时序行为或在设计投入生产之前保证这种时序行为变得越来越困难。为了避免制造速度放缓，该行业需要新的硅后验证和诊断工具，以有效解决设计模型及其在硅芯片上的实现之间的不一致性。为了应对这一挑战，PI提出了新的统计方法，可以更好地建模，更准确地模拟设备的时序行为。PI在该项目中提出了三个研究组成部分，与他们计划的教育活动相结合：（1）时序问题的诊断，（2）后硅验证和调试，以及（3）时序质量的预测。在诊断方面，将开发技术来定位故障芯片上的时序问题，确定这些问题是否可能是由于制造缺陷造成的。在验证和调试中，将开发技术以确保用于设计芯片的模型的时序行为与在制造过程中观察到的时序行为之间的一致性。对于第三个组成部分，定时质量的预测，技术将被开发，以得出关于大规模生产阶段的定时质量水平的统计推断。拟议的研究将补充其他研究工作的DSM电路和工艺变化的建模，采取更抽象的层次的分析。所提出的工具不是直接处理晶体管和导线，而是对相关的随机变量进行操作，这些随机变量对晶体管和导线的时序行为进行建模。该项目将促进为大型和复杂设计开发实用工具。当提出的统计工具和方法变得可用时，芯片设计者可以放松各种参数的度量，以获得最佳的设计折衷，从而将制造技术推向前沿。当硅的时序问题能够被更有效地检测和更好地理解时，公司就可以避免浪费资源来应对制造的不确定性，并将这些资源投入到更高效的用途中。