CPA: Reconfigurable On-chip Network Design Framework for Fault-Tolerance and Performance

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Reconfigurable On-chip Network Design Framework for Fault-Tolerance and Performance Traditional fault-tolerant interconnection network design typically assumes a coarse-grain fault model where entire links and/or routers are faulty. Solutions to the coarse-grain fault model broadly focus on topology-based routing-path redundancy or designing robust network protocols to detect and avoid faults. This coarse-grain fault model is appropriate for multicomputer networks, LANs and WANs where computers/hosts and the communication links are unreliable. However, the coarse-grain model is unsuitable for on-chip networks in which the common faults are (a) transient faults, (b) manufacture-time permanent faults and (c) permanent faults that occur over the lifetime of the integrated chip. This project has two aims. First, it aims to quantify the susceptibility of the various components of on-chip networks (i.e., buffers, routing logic, arbiters, switches and links) to the three classes of faults in terms of their architectural vulnerability factors (AVFs), yield-adjusted throughput and mean time to failure (MTTF). The second goal is to design protected and reconfigurable networks to minimize their vulnerability to faults and to provide mechanisms for graceful performance degradation when faults are navoidable.