Power-Efficient Reconfigurable Wireless Network-on-Chip (NoC) Interconnects for Future Many-core Architectures

点击翻译按钮获取中文摘要

The objective of this research is to improve the performance of future large-scale Network-on-Chips (NoCs) architectures by overcoming the limitations of excess power dissipation and increased latency observed in current metallic interconnects. The proposed approach is to exploit wireless technology to design power-efficient, reconfigurable, and scalable hybrid NoCs for future multi-cores.This proposal will evaluate novel wireless interconnects for NoCs and understand the interplay between power, performance and technology. The project will consist of architecture studies, evaluation of media access protocols and transceiver technologies, and performance modeling. The proposed architecture studies will encompass topology evaluation and shared-memory programming with the goal of reducing power and optimizing performance. The proposed media access studies will involve the development of reconfigurable protocols that adapt to the traffic fluctuations and change connectivity characteristics to improve performance. The proposed technology evaluation will uncover the capabilities as well as limitations of current technologies, and simultaneously evaluate novel materials/devices that can facilitate the design of the proposed wireless interconnects. The crosscutting nature of the proposed research will foster new research directions in several areas, spanning computer architecture, wireless communication and nanotechnology. Undergraduate and graduate students involved will get versatile training in several areas through the jointly administered courses. Minority and women students supervised by the investigators will directly participate in this project and the proposed outreach efforts will be organized by the diversity lead of the team. The results and findings of the proposed research will be disseminated to researchers and educators through technical publications and presentations.