Continuous Technology Management

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This project investigates Continuous Technology Management (CTM), the continuous runtime management of power dissipation, on-chip noise, particle strike vulnerability, process variations, and aging defects. In CTM, each processor core is divided into regions with integrated monitoring and test support, as well as the ability to push parameters (such as supply voltage) below worst case recommended limits. Guard bands are determined dynamically at runtime through a combination of localized stress testing and redundant safe operation on an adjacent unit with the same functionality. These guard bands should be almost always lower than can be achieved statically at design time and therefore can yield additional performance or power savings. Frequent periodic reassessment of guard bands permits the system to tolerate large, slow changes in environment (such as an increase in neutron flux with higher elevation) without having to resort to constant redundancy and its corresponding performance and power costs. This support is implemented in multiple layers comprising the hardware microarchitecture, monitor, diagnostic, and control (local and global controllers and system level middleware). The successful completion of this project will have broad implications for the U.S. semiconductor industry. The aforementioned challenges are serious obstacles to the ability to produce high performance, power efficient, robust computing platforms across the spectrum from handhelds to supercomputers.