Continuous Technology Management

本项目研究持续技术管理（CTM），持续运行时管理功耗、片上噪声、粒子撞击脆弱性、工艺变化和老化缺陷。在CTM中，每个处理器核心被划分为具有集成监控和测试支持的区域，以及将参数（如电源电压）推至最坏情况推荐限制以下的能力。保护带是在运行时动态确定的，通过结合局部压力测试和具有相同功能的相邻单元的冗余安全操作。这些保护带应该几乎总是低于在设计时可以达到的静态值，因此可以产生额外的性能或节省功率。对保护带进行频繁的定期重新评估，使系统能够承受环境中大而缓慢的变化（例如随着海拔的升高中子通量的增加），而不必诉诸于持续的冗余及其相应的性能和功率成本。这种支持在多个层中实现，包括硬件微体系结构、监视器、诊断和控制（本地和全局控制器以及系统级中间件）。该项目的成功完成将对美国半导体行业产生广泛的影响。上述挑战严重阻碍了从手持设备到超级计算机的高性能、高能效、健壮的计算平台的开发。

This project investigates Continuous Technology Management (CTM), the continuous runtime management of power dissipation, on-chip noise, particle strike vulnerability, process variations, and aging defects. In CTM, each processor core is divided into regions with integrated monitoring and test support, as well as the ability to push parameters (such as supply voltage) below worst case recommended limits. Guard bands are determined dynamically at runtime through a combination of localized stress testing and redundant safe operation on an adjacent unit with the same functionality. These guard bands should be almost always lower than can be achieved statically at design time and therefore can yield additional performance or power savings. Frequent periodic reassessment of guard bands permits the system to tolerate large, slow changes in environment (such as an increase in neutron flux with higher elevation) without having to resort to constant redundancy and its corresponding performance and power costs. This support is implemented in multiple layers comprising the hardware microarchitecture, monitor, diagnostic, and control (local and global controllers and system level middleware). The successful completion of this project will have broad implications for the U.S. semiconductor industry. The aforementioned challenges are serious obstacles to the ability to produce high performance, power efficient, robust computing platforms across the spectrum from handhelds to supercomputers.