Complexity-Adaptive Processors: Dynamic IPC/Critical Path Optimization

这项研究正在探索复杂性自适应处理器（CAPs），这是一种新的微架构，可以在运行时动态地进行硬件复杂性、延迟和时钟速度的权衡。CAPs为处理器和内存层次结构的主要硬件功能采用动态硬件结构。编译器、运行时系统或片上硬件可以修改这些结构的组织和延迟，以及芯片的时钟速度，以匹配应用程序的特性。该项目正在研究CAP设计方案，以评估该方法的性能潜力。具体工作包括：(1)调查各种应用程序的动态硬件需求；(2)评估CAP硬件结构的时序方面，包括变化延迟和时钟速度之间的权衡；(3)设计硬件与应用相匹配的配置调度策略；(4)评估动态时钟替代方案；(5)采用仿真与时序分析相结合的方法对CAPs方法的性能潜力进行量化。

This research is exploring Complexity-Adaptive Processors (CAPs), a new microarchitecture within which hardware complexity, latency, and clock speed tradeoffs can be made on-the-fly at runtime. CAPs employ dynamic hardware structures for the major hardware functions of the processor and memory hierarchy. The organization and delay of these structures, as well as the clock speed of the chip, can be modified by the compiler, runtime system, or on-chip hardware to match application characteristics. This project is investigating CAP design options in order to assess the performance potential of this approach. Specific tasks being carried out include: (1) Investigating the dynamic hardware requirements of a variety of applications; (2) Evaluating the timing aspects of CAP hardware structures, including the tradeoff between varying latency and clock speed; (3) Devising configuration scheduling strategies for matching the hardware to the application; (4) Evaluating dynamic clocking alternatives; (5) Using simulation coupled with timing analysis to quantify the performance potential of the CAPs approach.