SHF: Small: Dynamic Power Management in the Dark Silicon Era

SHF：小型：黑暗硅时代的动态电源管理

• 批准号: 1320545
• 负责人: David Albonesi
• 金额: $ 49.92万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-08-01 至 2019-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320545&HistoricalAwards=false
• 关键词: SHF; Small; Dynamic; Power; Management

Future heterogeneous multicore microprocessors are expected to be sopower constrained that not all transistors will be able to be poweredon at once. The general-purpose cores will be required to nimblyadapt to severely constrained power allocations when power is divertedto accelerators, and vice versa. In addition, energy-aware schedulingof threads to cores is becoming imperative as multicore architecturesbecome more heterogeneous. This research develops power gatedmulticore architectures and integrated scheduling and power allocationalgorithms for maximizing throughput given varying and potentiallystringent limits on allocated power.One facet of the research is the design, synthesis, and evaluation ofpower gated general-purpose and data-parallel acceleratormicroarchitectures comprised of deconfigurable lanes--horizontalslices through the pipeline--that permit dynamic tailoring of eachcore to the application. The goal is to demonstrate tolerableperformance and power-gating overheads yet flexibility in adapting toworkload behaviors. A second aspect of the work is a new optimizationapproach that efficiently finds a near-global-optimum configuration oflanes and thread-to-core assignment without requiring offline trainingor foreknowledge of the workload. The approach combines reducedsampling techniques, adaptation of response surface models to onlineoptimization, incorporation of limited online profiling information,and heuristic online search. The research will improve thecomputational capability of future severely power-constrained devices;involve undergraduate, graduate, and/or postdoc women engineers; andbe incorporated into computer architecture and heuristic optimizationclasses.

未来的异构型多核微处理器预计将受到功耗的限制，不是所有的晶体管都能同时通电。当电力被转移到加速器时，通用内核将被要求灵活地适应严格受限的功率分配，反之亦然。此外，随着多核体系结构变得更加异构化，对线程进行节能调度变得势在必行。这项研究开发了功率门多核体系结构以及集成的调度和功率分配算法，以便在给定对分配的功率的变化和潜在的严格限制的情况下最大化吞吐量。研究的一个方面是功率门通用和数据并行加速器微体系结构的设计、综合和评估，该微体系结构由可取消配置的通道组成--流水线中的水平切片--允许根据应用动态地定制每个核心。我们的目标是展示可接受的性能和电源门控开销，以及适应工作负载行为的灵活性。这项工作的第二个方面是一种新的优化方法，它可以有效地找到接近全局最优的扇区配置和线程到内核的分配，而不需要离线培训或预先知道工作量。该方法结合了简化抽样技术、响应面模型适应在线优化、合并有限的在线侧写信息和启发式在线搜索。这项研究将提高未来严重电力受限设备的计算能力；涉及本科生、研究生和/或博士后女工程师；并将被纳入计算机体系结构和启发式优化课程。