SHF: Small: Dynamic Power Management in the Dark Silicon Era

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Future heterogeneous multicore microprocessors are expected to be sopower constrained that not all transistors will be able to be poweredon at once. The general-purpose cores will be required to nimblyadapt to severely constrained power allocations when power is divertedto accelerators, and vice versa. In addition, energy-aware schedulingof threads to cores is becoming imperative as multicore architecturesbecome more heterogeneous. This research develops power gatedmulticore architectures and integrated scheduling and power allocationalgorithms for maximizing throughput given varying and potentiallystringent limits on allocated power.One facet of the research is the design, synthesis, and evaluation ofpower gated general-purpose and data-parallel acceleratormicroarchitectures comprised of deconfigurable lanes--horizontalslices through the pipeline--that permit dynamic tailoring of eachcore to the application. The goal is to demonstrate tolerableperformance and power-gating overheads yet flexibility in adapting toworkload behaviors. A second aspect of the work is a new optimizationapproach that efficiently finds a near-global-optimum configuration oflanes and thread-to-core assignment without requiring offline trainingor foreknowledge of the workload. The approach combines reducedsampling techniques, adaptation of response surface models to onlineoptimization, incorporation of limited online profiling information,and heuristic online search. The research will improve thecomputational capability of future severely power-constrained devices;involve undergraduate, graduate, and/or postdoc women engineers; andbe incorporated into computer architecture and heuristic optimizationclasses.