Collaborative Research: CRS--AES: SoftCheck: Compiler and Run-Time Technology for Efficient Fault Detection and Correction in Low nm-Scale Multicore Chips

CSR-AES：合作研究：软检查：本项目的目标是开发灵活高效的并行和并行系统（RCS）技术，以经济高效地检测即将到来的多核芯片中的硬件故障并从故障中恢复。 半导体变化、温度热点、软错误和老化将使硬件可靠性成为多核处理器设计中的核心问题之一。RCS技术由于其灵活性、低成本和针对影响程序结果的错误的能力，将使应对这一挑战成为可能。该项目的两个重要目标是：（1）避免线程内或线程间的完整指令复制，这是能源和成本意识商品市场接受的关键;（2）提供旋钮来选择所需的性能与错误覆盖率的权衡。将为评价目的实施一个原型软件检查。广泛的新颖的，具有成本效益的故障检测和纠正技术将被设计和实施SoftCheck。故障检测技术将包括：（i）穷举自检，（ii）部分自检，（iii）多核环境中的部分跨线程检查，以及（iv）其他横切，通常与多处理器相关的方法。错误校正技术包括：（i）禁用核心中的集群（ii）禁用完整的核心，以及（iii）动态重新编译以使用其他硬件。

CSR---AES: Collaborative Research: SoftCheck: Compiler and Run-Time Technology for Efficient Fault Detection and Correction in Low nm-Scale Multicore ChipsThe goal of this project is to develop flexible and efficient Runtime and Compiler System (RCS) technologies to cost-effectively detect and recover from hardware faults in upcoming multicore chips. Semiconductor variations, temperature hot spots, soft errors and aging will make hardware reliability one of the central concerns in the design of multicore processors. RCS technologies will make it possible to meet this challenge because of their flexibility, low cost and ability to target errors that affect program outcome. Two important objectives of this project are: (1) to avoid full instruction replication within or across threads this is key to acceptance in the energy- and cost-conscious commodity markets and (2) to provide knobs to select the desired performance vs. error-coverage tradeoff. A prototype, SoftCheck, will be implemented for evaluation purposes. A wide range of novel, cost-effective fault detection and correction techniques will be designed and implemented in SoftCheck. The fault-detection techniques will include: (i) exhaustive self-checking, (ii) partial self-checking, (iii) partial cross-thread checking in a multicore environment, and (iv) other cross-cutting, often multiprocessor-related, approaches. The fault-correction techniques include: (i) disabling clusters in a core (ii) disabling complete cores, and (iii) dynamic recompilation to use other hardware.