SGER: Scalability of Hetero-Nanocrystal Memory

SGER：异质纳米晶体存储器的可扩展性

• 批准号: 0622647
• 负责人: Jianlin Liu
• 金额: $ 6万
• 依托单位: University of California-Riverside
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-05-01 至 2007-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0622647&HistoricalAwards=false
• 关键词: SGER; Scalability; Hetero; Nanocrystal; Memory

Intellectual Merit:Similar to logic devices, flash memories based on extended floating gate are scaling down following Moore's Law and running into limit at about 45nm technology node because of the tunneling oxide thickness scaling limit. We propose to use hetero-nanocrystals to replace the extended silicon layer as a floating gate for nonvolatile applications beyond the 45nm technology node. The important reason behind the utilization of the hetero-nanocrystal floating gate is that hetero-nanocrystals can introduce a deeper well with an additional barrier for long-retention charge storage and keep fast writing/erasing speed at lower operation voltage in a scaled device. Through this exploratory research project, we will prove the scalability of hetero-nanocrystal memory toward CMOS ultimate limit. The specific plan is 1) to simulate scaled memory devices containing dot variations using 3-D NEMO codes to prove that the same number of charges and the collective effect of these charges rather than dot density/size variation play dominant role in determining device performance across a wafer, and 2) to experimentally conduct self-assembled growth of silicon dots onto small SiO2/Si patterns with dimensions corresponding to beyond-45nm scaled technology nodes to achieve well-controlled dot statistics. The resources from the PI's Quantum Structures Laboratory, the PI's ongoing collaboration, and the university's new nanofabrication facility are ready to be used to explore these goals. This research will enrich the state-of-the-art knowledge on nanostructures and help to discover more principles of the bottom-up nanofabrication technique: Self-assembly. In addition, the incorporation of hetero-nanocrystals into MOSFET memory devices will also enrich the knowledge of nanoelectronic devices. It will help to explain the unusual electrical transport characteristics in hetero-nanostructures. Finally, the project will also add to the core knowledge of the technologically important material systems of silicon and silicide.Broader Impact:The proposed work on the scalability of hetero-nanocrystal memories, if successfully demonstrated, will extend the nonvolatile memory scaling limits and be used by the electronic memory industry to produce better devices than present commercialized ones to benefit people's daily lives. The net benefit to memory companies and civilians will be tremendous, beyond the point (compared with present nonvolatile memory of more than $10 billion market) that could be estimated. The project will also train a graduate student to gain valued experiences from memory device simulations to nanofabrication techniques such as self-assembly. To have even broader impact, the PI will disseminate the successful research results to K-12 students through ongoing UCR summer programs in nanotechnology, which are designed to increase the number and diversity of students pursuing studies and careers in science and engineering fields. This can be achieved through a 2-hour lecture to high-school students and middle-school students on nanotechnology and the relationship between memory and cell phones/digital cameras in the end of this project. Moreover, multiple group visits to research laboratory from local school districts will be arranged at the UCR's Chancellor scholarship day. These educational modules will foster science and engineering interest in these K-12 students.

智力优势：与逻辑器件类似，基于扩展浮栅的闪存正遵循摩尔定律按比例缩小，并且由于隧穿氧化物厚度缩放限制而在约45 nm技术节点处遇到限制。我们建议使用异质纳米晶体来取代扩展的硅层作为浮栅，用于45纳米技术节点以外的非易失性应用。异质结浮栅的重要原因是异质纳米晶体可以引入更深的阱，并具有用于长保留电荷存储的额外势垒，并且在缩放的器件中在较低的操作电压下保持快速的写入/擦除速度。通过这个探索性的研究项目，我们将证明异质结存储器向CMOS极限的可扩展性。具体计划是1）使用3-D NEMO代码来模拟包含点变化的缩放存储器器件，以证明相同数量的电荷和这些电荷的集体效应而不是点密度/尺寸变化在确定整个晶片上的器件性能中起主导作用，以及2）实验性地进行硅点在小的SiO2/Si图案上的自组装生长，所述小的SiO2/Si图案具有对应于超过-45纳米缩放技术节点，实现良好控制的网点统计。来自PI量子结构实验室的资源，PI正在进行的合作，以及该大学新的纳米制造设施已准备好用于探索这些目标。这项研究将丰富纳米结构的最新知识，并有助于发现自下而上纳米纤维技术的更多原理：自组装。此外，异质纳米晶体在MOSFET存储器件中的应用也将丰富纳米电子器件的知识。这将有助于解释异质纳米结构中不寻常的电输运特性。最后，本项目还将增加硅和硅化物这一重要技术材料系统的核心知识。更广泛的影响：如果成功展示异质结存储器的可扩展性，将扩展非易失性存储器的扩展限制，并被电子存储器行业用于生产比目前商业化的设备更好的设备，以造福人们的日常生活。存储器公司和平民的净收益将是巨大的，超出了可以估计的点（与目前超过100亿美元的非易失性存储器市场相比）。该项目还将培训一名研究生，以获得从存储设备模拟到纳米纤维技术（如自组装）的宝贵经验。为了产生更广泛的影响，PI将通过正在进行的UCR纳米技术暑期课程向K-12学生传播成功的研究成果，该课程旨在增加在科学和工程领域从事研究和职业的学生的数量和多样性。这可以通过在本项目结束时为高中生和中学生举办关于纳米技术以及存储器与手机/数码相机之间关系的2小时讲座来实现。此外，在UCR的校长奖学金日，当地学区将安排多个团体参观研究实验室。这些教育模块将培养这些K-12学生对科学和工程的兴趣。