CAREER: Modeling Data Locality For Next Generation Systems

虽然多核系统的引入提高了处理器的整体速度，但没有显著提高CPU时钟频率，但CPU核心和主内存之间的速度差距仍然很大。长期以来，多级缓存一直被用来弥合这一差距。传统的高速缓存设计偏爱具有良好局部性的应用程序。然而，社区对地方的理解更多的是定性的，而不是定量的。对局部性的定量理解对于开发内存层次结构和实现最大性能至关重要。新一代多核系统增加了多线程程序量化数据局部性的挑战，该研究依赖于编译器、分析器和硬件实时监控之间的密切合作，将数据局部性建模为三个参数的函数：数据大小、路径历史和线程计数。编译器提供程序的全局视图。分析器使用跟踪来查看程序的运行时行为，但该视图仅基于有限数量的训练输入。尽管硬件的视图是特定于运行的，但由于缓冲区大小的限制，其预测通常取决于硬件缓冲区，并不总是有效的。正在开发的协作模型结合了静态分析和运行时采样和剖析的优点，为单线程和多线程程序提供了准确的程序局部性视图。基于该模型，该项目探索了内存系统的性能，包括管理传统多级缓存和非统一缓存架构(NUCA)缓存中的数据移动，减少最先进的纯硬件区域预取器的内存流量，以及改善Java程序的空间局部性。

Although the introduction of multi-core systems has increased overall processor speed without significantly increasing CPU clock rates, a significant speed disparity remains between the CPU core and main memory. Multi-level caches have long been used to bridge this gap. Conventional cache design favors applications with good locality. The community's understanding of locality, however, is more qualitative than quantitative. A quantitative understanding of locality is essential to exploit memory hierarchy and achieve maximal performance. The new generation of multi-core systems adds the challenge of quantifying data locality for multi-threaded programs.This research models data locality as a function of three parameters: data size, path history, and thread count, relying on close cooperation among the compiler, the profiler, and hardware just-in-time monitoring. The compiler provides a global view of the program. The profiler, using traces, has a view of the run-time behavior of a program, but this view is based on only a limited number of training inputs. Although the hardware's view is run specific, its prediction, often depending on hardware buffers, is not always effective due to buffer size limitations. The cooperative model being developed combines the advantages of static analysis and run-time sampling and profiling, providing an accurate view of program locality for both single-threaded and multi-threaded programs. Given this model the project explores memory system performance including managing data movement in conventional multi-level cache as well as non-uniform cache architecture (NUCA) caches, reducing the memory traffic of a state-of-the-art hardware-only region prefetcher, and improving spatial locality of Java programs.