CAREER: Modeling Data Locality For Next Generation Systems

职业：为下一代系统建模数据局部性

• 批准号: 0643664
• 负责人: Zhenlin Wang
• 金额: $ 31.7万
• 依托单位: Michigan Technological University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-04-15 至 2015-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0643664&HistoricalAwards=false
• 关键词: CAREER; Modeling; Data; Locality; Next

Although the introduction of multi-core systems has increased overall processor speed without significantly increasing CPU clock rates, a significant speed disparity remains between the CPU core and main memory. Multi-level caches have long been used to bridge this gap. Conventional cache design favors applications with good locality. The community's understanding of locality, however, is more qualitative than quantitative. A quantitative understanding of locality is essential to exploit memory hierarchy and achieve maximal performance. The new generation of multi-core systems adds the challenge of quantifying data locality for multi-threaded programs.This research models data locality as a function of three parameters: data size, path history, and thread count, relying on close cooperation among the compiler, the profiler, and hardware just-in-time monitoring. The compiler provides a global view of the program. The profiler, using traces, has a view of the run-time behavior of a program, but this view is based on only a limited number of training inputs. Although the hardware's view is run specific, its prediction, often depending on hardware buffers, is not always effective due to buffer size limitations. The cooperative model being developed combines the advantages of static analysis and run-time sampling and profiling, providing an accurate view of program locality for both single-threaded and multi-threaded programs. Given this model the project explores memory system performance including managing data movement in conventional multi-level cache as well as non-uniform cache architecture (NUCA) caches, reducing the memory traffic of a state-of-the-art hardware-only region prefetcher, and improving spatial locality of Java programs.

虽然多核系统的引入提高了整体处理器速度，但没有显著提高CPU时钟速率，但CPU内核和主存之间仍然存在显著的速度差距。多级缓存长期以来一直被用来弥补这一差距。传统的缓存设计有利于具有良好局部性的应用程序。 然而，社区对地方性的理解更多的是定性而不是定量。 对局部性的定量理解是利用存储层次结构和实现最大性能的必要条件。 新一代多核系统增加了量化多线程程序数据局部性的挑战，本研究将数据局部性建模为三个参数的函数：数据大小、路径历史和线程数，依赖于编译器、分析器和硬件实时监控之间的密切合作。 编译器提供程序的全局视图。使用跟踪的分析器具有程序的运行时行为的视图，但是该视图仅基于有限数量的训练输入。虽然硬件的视图是运行特定的，但由于缓冲区大小的限制，其预测通常取决于硬件缓冲区，并不总是有效的。 正在开发的合作模型结合了静态分析和运行时采样和分析的优点，提供了一个准确的视图的程序本地单线程和多线程程序。 鉴于此模型，该项目探讨了内存系统的性能，包括管理传统的多级缓存以及非均匀缓存架构（NUCA）缓存中的数据移动，减少最先进的硬件区域预取器的内存流量，并提高Java程序的空间局部性。