Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design

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Designing robust and energy-efficient large-scale systems-on-chips (SOCs) with high design productivity is a challenge of great interest. However, lack of coordination among different design layers has caused designers to make worst-case assumptions at individual design layers, leading to substantially suboptimal designs with poor reliability/energy/performance co-optimization or tradeoffs. This project is the first major effort dedicated toward a unified failure-resistant system from high-level synthesis to physical design with tight integration. It will build reliability-centric physical-aware high-level synthesis and high-level-guided physical design to bridge the gap between these two distant layers. A novel cross-layer engineering change order (ECO) framework will also be developed to couple high-level ECO with stable physical-level ECO. New tools and methodologies will be studied and provided to the system and physical design community targeting reliability while increasing overall design productivity and quality. Electronics have permeated modern society, which increasingly depends on reliable operations of these electronic systems. However, device-level scaling is heading in the opposite direction from system reliability. This project will transform existing SOC design methodologies through cross-layer integration. Research from this effort will be broadly disseminated through publications and presentations, active interaction with industrial collaborators, as well as infusion of new course material into classrooms and instructional laboratories. The principal investigators will continue their efforts in recruiting women and other underrepresented minorities into their research programs. They have previously reached out to K-12 students and will continue to do so in order to attract the best of them into the engineering profession.