MixedCoreSoC - A Highly Dependable Self-Adaptive Mixed-Signal Multi-Core System-on-Chip

未来的嵌入式片上系统（SoC）将必须满足即将到来的应用和硬件平台提出的几个新要求：由于集成密度增加导致的工艺可靠性降低和器件老化，在不可靠的硬件存在下的高可靠性将成为一个关键特征。为了适应不断变化的硬件平台和不断变化的环境，自适应是必要的。模拟器件的重要性日益增加，需要混合信号处理。实时性要求、自适应性和硬件不可靠性是另一个设计挑战，因此，我们提出了一种混合核SoC架构，该架构由一个广义核和任务概念以及一个人工激素系统（AHS）组成，以满足这些要求。在第一个项目阶段，我们开发了架构的关键概念，并通过仿真验证了这些概念。在本建议书要求的第二个项目阶段，我们重点关注四个主要问题：第一，我们希望通过增加可靠的嵌入式控制接口和核心间通信网络来完成系统设计。此外，将考虑人工激素系统的故障。这些方面在项目第一阶段被有意忽略。混合信号任务迁移也是一个特别的重点。第二，可预测的可靠性是预见的，因为它是一个嵌入式实时应用程序的关键功能。因此，将对可靠性和可预测性参数进行详细分析，以量化所达到的可靠性增益，并保证可用性和最坏情况下的延迟作为故障率的函数。此外，统计故障的措施，如MTTF和产量增加将被导出。可靠性、实时性和能耗之间的权衡是另一个需要研究的方面。第三，将建立一种使用MixedCoreSoC架构开发应用程序的设计方法。由于设计空间的多样性，支持用户选择MixedCoreSoC架构的重要设计参数至关重要。因此，设计流程，以合成一个具体的可靠的系统与所需的性能在给定的技术设想。第四，从纯仿真到基于原型和真实世界应用场景的扩展评估的步骤被提供，以确认和深化所取得的结果，并解决模拟中难以覆盖的方面，例如，相对于外围传感器/执行器组件的实时行为或能源相关问题。因此，MixedCoreSoC架构的原型实现与真实的演示器应用相结合。在此基础上，将对性能、可靠性、可预测性和成本进行详细评估，所提出的项目符合优先级计划1500的框架，因为它通过使用生物启发的操作原理和相应的设计方法的创新硬件架构，大大有助于提高嵌入式系统的可靠性。

Future embedded Systems on Chip (SoC) will have to meet several new requirements given by upcoming applications and hardware platforms: High dependability in the presence of unreliable hardware will be a key feature due to degrading process reliability and device ageing caused by increasing integration density. Selfadaptation is necessary to adapt to a changing hardware platform and changing environment. The increasing importance of analog parts requires mixed-signal processing. Real-time requirements in combination with self-adaptation and unreliable hardware are another design challenge.Therefore, we proposed the MixedCoreSoC architecture being composed of a generalized core and task concept in combination with an artificial hormone system (AHS) to meet these requirements. In the first project phase we developed the key concepts of the architecture and validated these concepts by simulation. In the second project phase requested in this proposal, we focus on four major issues:First, we want to complete the system design by adding reliable hormone-controlled interface and inter-core communication networks. Furthermore, failures in the artificial hormone system will be considered. These aspects have been intentionally left out in the first project phase. A special focus is also set on mixed signal task migration.Second, predictable dependability is envisioned as it is a key feature for embedded real-time applications. So a detailed analysis of the dependability and predictability parameters will be conducted to quantify the dependability gain reached and to allow guarantees on availability and worst-case delay as a function of failure rates. Furthermore, statistic failure measures like MTTF and yield increase will be derived. The trade-off between reliability, real-time properties and energy consumption is another aspect to be investigated.Third, a design methodology for developing applications using the MixedCoreSoC architecture will be established. Due to the variety of the design space, support for a user in selecting vital design parameters of the MixedCoreSoC architecture is essential. Therefore, a design flow to synthesize a concrete dependable system with desired properties on a given technology is envisioned. A toolkit for an iterative optimization of the design decisions would also be helpful.Fourth, the step from pure simulation to an extended evaluation based on a prototype and a real-world application scenario is provided to confirm and deepen the achieved results and to address aspects hard to cover in simulation like e.g. real-time behavior with respect to peripheral sensor/actor components or energy related issues. Therefore, a prototypic implementation of the MixedCoreSoC architecture in combination with a real demonstrator application is intended. Based on this, a detailed evaluation of performance, dependability, predictability and costs will be performed.The proposed project fits the frame of the priority programme 1500, because it substantially contributes to increase the dependability of embedded systems by an innovative hardware architecture using a biologically inspired operation principle and a corresponding design method.