CSR---SMA: Variability-Aware System Level Performance and Power Analysis

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Current high-level design methodologies and tools assume a classic static timing behavior and do not include effects of design variability on performance or energy. In support of a complete probabilistic design flow, high-level modeling of variability effects is needed for determining design choices that are most likely to meet initial design constraints. This project enables high-level analysis of design variability on overall system performance and power consumption. The problem of performance and power analysis is addressed for both latency- and throughput-constrained applications mapped onto platforms characterized by either globally synchronous or asynchronous on-chip communication. The research provides a comprehensive framework that includes (i) probabilistic latency, rate, and leakage analysis in the presence of variations; and (ii) design exploration capabilities for determining early in the design process the design choices more likely to meet prescribed performance or leakage power limits. An integral component of the project is its impact on educational activities at Carnegie Mellon University, as well as its overall societal impact via enabling frontier application development. Without a strong foundation for training next generation''s system designers and computer architects, the achievement of aggressively scaled integrated system will not be possible. The proposed variability modeling framework (which will be distributed freely) can be used for the design of next generation Systems-on-Chip, thereby enabling applications having a broad societal impact. More precisely, complex systems that seamlessly integrate homogeneous or heterogeneous cores and have predictable performance and power budgets will most likely find their applications in large segments of the consumer market.